Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Subject: Re: [PATCH 1/1] pinctrl: amd: disable and mask interrupts on probe
To:     Sachi King <nakato@nakato.io>, linux-gpio@vger.kernel.org,
        basavaraj.natikar@amd.com
Cc:     linux-kernel@vger.kernel.org,
        "Limonciello, Mario" <mario.limonciello@amd.com>,
        Shyam-sundar S-k <Shyam-sundar.S-k@amd.com>,
        "Shah, Nehal-bakulchandra" <Nehal-bakulchandra.Shah@amd.com>
References: <20211001161714.2053597-1-nakato@nakato.io>
 <20211001161714.2053597-2-nakato@nakato.io>
From:   Basavaraj Natikar <bnatikar@amd.com>
Message-ID: <5d683882-257d-87b2-20aa-0871e2902090@amd.com>
Date:   Sat, 9 Oct 2021 01:27:16 +0530
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101
 Thunderbird/78.14.0
In-Reply-To: <20211001161714.2053597-2-nakato@nakato.io>
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 7bit
Content-Language: en-US
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?TTBhY0NlQkw1aFFnSkdKNW1qTlBQbEJRejBkelphbkJhV2VlODZFTitWVzRs?=
 =?utf-8?B?RXZOeEV2QWQ1ckp1VGE2WU5NQjBRaFprajJKVzNuWXg2UXIwZEJldG9BUGJw?=
 =?utf-8?B?L3ZvSWNsRmFEa2k3eGdYVnBhcGl1SjZ6YnliaTljTnQ2aUVjV3cwNCs3Mmpl?=
 =?utf-8?B?TWZ2NUVZYmZLYW5aR3JqYmx4NlRDalIrZ2tEU0VuVTFoQUhaNXVjdVZKTCs1?=
 =?utf-8?B?R3VzK1psMVA3MjZsQjg3bjZPcDFQVnhUU3hGQWtib1VDYWt0YmlBaHdqdUhm?=
 =?utf-8?B?R3hYdUd2ZUMvSGc3cmhmZE4valBCTGN4bHVvbi8xVER2S2M3TW9uMC9WMXJK?=
 =?utf-8?B?NmZEbkt5UVBYVDcrS3ZkcFB6dUpkQTdvNUFiZnhDR1lncHlBdTlXbmt0TC8r?=
 =?utf-8?B?QXoxR3ZKTTJXSWpMUlRaVVpQYU5ZcmpXc2lwU3F5MHBWb0dkNUwxZzRqaWtG?=
 =?utf-8?B?Vnk0K2trZFRNOW1CbHpwT2RDdyttaWo0NlZFNVdSS0l2dFNiQW9XZmpnODBQ?=
 =?utf-8?B?R1g1S3dmUUsxQjdqZGtUVWM1ZzFqVHYxblo1WkRyZWd1YUtTNVBGMTRCVHpz?=
 =?utf-8?B?OWpxdjNOdmNnSTVIZGV3RjN2dmNwYVp2VWJGaHlpRHpvNFhFbHhkTUM3c2g2?=
 =?utf-8?B?SktqUFpBUXhhRGN0NGIzZ1pCaUU1R0ZvaGNZQXpjUlBQWUJldkxOTUFhMXp6?=
 =?utf-8?B?QXFDQ1pieTFFVWpSZjRvRmlWK1JEYndxZk5hU3hRY3c3SFBZdlBUV2tJNVVa?=
 =?utf-8?B?dEphdnNqWjF4eFgrcjhMWFBFSWxaQlR5TFg2MkFPdk5aaHdoY1RZRmlhbGZD?=
 =?utf-8?B?VW83U3l4eGcwaldDa1duN2h2RGlSWUFYcHZPVEtiMkhwT29oVW9kV0tSaE4y?=
 =?utf-8?B?WlROdGFBNFFtK1Vkd052ZVZDMGJyNUYxV1ZJU1lwWGlRQVVqR3lEVHJaOS9Y?=
 =?utf-8?B?dDJFTmVIZEw5MmtVSStWTGhRaVpJRzFmQ3RKOWVUL2RVN1dReDROaWh0NW1J?=
 =?utf-8?B?QWpQaHlRWExsbTlRYmdiWmx0ZjR3cnBKUkVXWjk0bG1SNTFUN3Byb2lKclBF?=
 =?utf-8?B?aTNRTE02QjJaY1lNbE9acXdmVW93SUY1S3JkMjlLTXVSWVZSejFZRk5SVzhx?=
 =?utf-8?B?YmNpWTVzeFpsMDh4OVh0MGZvOHI0WWVuZ3J6aWhlcU9pNDYyZXFqeThobFBo?=
 =?utf-8?B?Q3FVWEovUldGclQwMjQzeHovL0xLU1hjcFErd0tMeWVMb0sxdlBvNTNiVWl4?=
 =?utf-8?B?WTFrMTR5TjBlUTRNbjhVRHBVd3plbkUwc1VkeUpzVXZsam82VmNyaUlDVUpi?=
 =?utf-8?B?aGF3M2gzSDJWc0FVY0tRV2sxZllNOTNCT0ZvVWkwV0F1M3kyaTJQdFVXSjZF?=
 =?utf-8?B?SDQ3ME5VYUFZcEZycDQxaWloK3IyNW1Dc3d4cVNJQmRydXdWQTFrTG94b243?=
 =?utf-8?B?cGpqN0VOWTZVK212Z0JwRkNKM2V5VXFWVnZjRjBEbWRrd1NGQzJ0NThnbm1h?=
 =?utf-8?B?VFJ2cTlWalQ5ZndxTk1oUzVIcUo2SXYzNGswTmNiMWVyZmNpMERhTVZyWTBC?=
 =?utf-8?B?bWwvbVIySkl6TjBiaTJ4blFsODlPclNkeThHbEg5K0hkVmFrWDRrQWVaNjBs?=
 =?utf-8?B?NldadjZEOFlDZTFMUUtucHFpRHVyb1c2cWgvMHRNYjBKd29DMHdqOGNHSDNi?=
 =?utf-8?B?amg1RlpSNkpNU3pBN0IyMXFYTUszYlF6Sy9mT1VlcWNFZlBvZ2NxSkdqclVL?=
 =?utf-8?B?RHlkdUZ1M2E4Rm5GTS83N0lOWnhJTElWNVBjRTBoOGJ5em9GOUV3SmdEdTBW?=
 =?utf-8?B?d1liaDRQVU5QdjNMNE4wbjNaMGhrblc2UTJlYmFXZ253dHNOQjkwZVFIeGMz?=
 =?utf-8?Q?V7bg9k5K914RL?=
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 34c7a983-4bef-4c63-243d-08d98a95dad7
X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5040.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2021 19:57:27.7242
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 6NfpNjUjjl13CgYp0jtyAJz1vH1VzpDL1mEkr2p0VLEBo7V8R81+PbqSsnSObyHWiuU/GjqFdCfiSdQ0ndklUw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5357
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 10/1/2021 9:47 PM, Sachi King wrote:
> [CAUTION: External Email]
>
> Some systems such as the Microsoft Surface Laptop 4 leave interrupts
> enabled and configured for use in sleep states on boot, which cause
> unexpected behaviour such as spurious wakes and failed resumes in
> s2idle states.
>
> As interrupts should not be enabled until they are claimed and
> explicitly enabled, disabling any interrupts mistakenly left enabled by
> firmware should be safe.
>
> Signed-off-by: Sachi King <nakato@nakato.io>
> ---
>  drivers/pinctrl/pinctrl-amd.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
> index c001f2ed20f8..aa4136cd312d 100644
> --- a/drivers/pinctrl/pinctrl-amd.c
> +++ b/drivers/pinctrl/pinctrl-amd.c
> @@ -830,6 +830,32 @@ static const struct pinconf_ops amd_pinconf_ops = {
>         .pin_config_group_set = amd_pinconf_group_set,
>  };
>
> +static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) {
> +       struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
> +       unsigned long flags;
> +       u32 pin_reg, mask;
> +       int i;
> +
> +       mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3)
> +               | BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF)
> +               | BIT(INTERRUPT_MASK_OFF) | BIT(WAKE_CNTRL_OFF_S4);

Could you please correct INTERRUPT_MASK_OFF , added twice.

Thanks,
Basavaraj 

> +
> +       for (i = 0; i < desc->npins; i++) {
> +               int pin = desc->pins[i].number;
> +               const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
> +               if (!pd)
> +                       continue;
> +
> +               raw_spin_lock_irqsave(&gpio_dev->lock, flags);
> +
> +               pin_reg = readl(gpio_dev->base + i * 4);
> +               pin_reg &= ~mask;
> +               writel(pin_reg, gpio_dev->base + i * 4);
> +
> +               raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
> +       }
> +}
> +
>  #ifdef CONFIG_PM_SLEEP
>  static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
>  {
> @@ -967,6 +993,9 @@ static int amd_gpio_probe(struct platform_device *pdev)
>                 return PTR_ERR(gpio_dev->pctrl);
>         }
>
> +       /* Disable and mask interrupts */
> +       amd_gpio_irq_init(gpio_dev);
> +
>         girq = &gpio_dev->gc.irq;
>         girq->chip = &amd_gpio_irqchip;
>         /* This will let us handle the parent IRQ in the driver */
> --
> 2.33.0
>