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From:   Adam Ford <aford173@gmail.com>
Date:   Sat, 9 Oct 2021 09:46:33 -0500
Message-ID: <CAHCN7x+81JrpA8MenzDby8OjjCJqu9nt0JbtE7opsLxO1+RbfQ@mail.gmail.com>
Subject: Re: [PATCH 3/7] soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
To:     Lucas Stach <l.stach@pengutronix.de>
Cc:     arm-soc <linux-arm-kernel@lists.infradead.org>,
        Adam Ford-BE <aford@beaconembedded.com>,
        Rob Herring <robh+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        devicetree <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Wed, Oct 6, 2021 at 2:45 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Am Dienstag, dem 05.10.2021 um 19:05 -0500 schrieb Adam Ford:
> > This adds the description for the i.MX8MN disp blk-ctrl.
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> > ---
> >  drivers/soc/imx/imx8m-blk-ctrl.c | 70 ++++++++++++++++++++++++++++++++
> >  1 file changed, 70 insertions(+)
> >
> > diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
> > index e172d295c441..8fcd5ed62f50 100644
> > --- a/drivers/soc/imx/imx8m-blk-ctrl.c
> > +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> > @@ -14,6 +14,7 @@
> >  #include <linux/clk.h>
> >
> >  #include <dt-bindings/power/imx8mm-power.h>
> > +#include <dt-bindings/power/imx8mn-power.h>
> >
> >  #define BLK_SFT_RSTN 0x0
> >  #define BLK_CLK_EN   0x4
> > @@ -498,6 +499,75 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = {
> >       .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),
> >  };
> >
> > +
> > +static int imx8mn_disp_power_notifier(struct notifier_block *nb,
> > +                                   unsigned long action, void *data)
> > +{
> > +     struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
> > +                                              power_nb);
> > +
> > +     if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
> > +             return NOTIFY_OK;
> > +
> > +     /* Enable bus clock and deassert bus reset */
> > +     regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
> > +     regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
> > +
> > +     /*
> > +      * On power up we have no software backchannel to the GPC to
> > +      * wait for the ADB handshake to happen, so we just delay for a
> > +      * bit. On power down the GPC driver waits for the handshake.
> > +      */
> > +     if (action == GENPD_NOTIFY_ON)
> > +             udelay(5);
> > +
> > +
> > +     return NOTIFY_OK;
> > +}
> > +
> > +static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
> > +     [IMX8MN_DISPBLK_PD_MIPI_DSI] = {
> > +             .name = "dispblk-mipi-dsi",
> > +             .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
> > +             .num_clks = 2,
> > +             .gpc_name = "mipi-dsi",
> > +             .rst_mask = BIT(0) | BIT(1),
> > +             .clk_mask = BIT(0) | BIT(1),
> > +     },
> > +     [IMX8MN_DISPBLK_PD_MIPI_CSI] = {
> > +             .name = "dispblk-mipi-csi",
> > +             .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
> > +             .num_clks = 2,
> > +             .gpc_name = "mipi-csi",
> > +             .rst_mask = BIT(2) | BIT(3),
> > +             .clk_mask = BIT(2) | BIT(3),
> > +     },
> > +     [IMX8MN_DISPBLK_PD_LCDIF] = {
> > +             .name = "dispblk-lcdif",
> > +             .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
> > +             .num_clks = 3,
> > +             .gpc_name = "lcdif",
> > +             .rst_mask = BIT(4) | BIT(5),
> > +             .clk_mask = BIT(4) | BIT(5),
> > +     },
> > +     [IMX8MN_DISPBLK_PD_ISI] = {
> > +             .name = "dispblk-isi",
> > +             .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
> > +                                             "disp_apb_root"},
> > +             .num_clks = 2,
>
> I think those are wrong. At least the num_clks and the number of clock
> names is inconsistent.

The NXP tree shows 4 clocks on the ISI node are enabled before the ISI
can be pulled out of reset.  I'll make the num_clks = 4.

>
> > +             .gpc_name = "isi",
> > +             .rst_mask = BIT(6) | BIT(7),
> > +             .clk_mask = BIT(6) | BIT(7),
> > +     },
> > +};
> > +
> > +static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
> > +     .max_reg = 0x84,
> > +     .power_notifier_fn = imx8mn_disp_power_notifier,
> > +     .domains = imx8mn_disp_blk_ctl_domain_data,
> > +     .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
> > +};
> > +
> You need to hook this up in imx8m_blk_ctrl_of_match, otherwise this is
> all just dead code.

Oops.  I had that, but i forgot to commit after the save.  It'll be
fixed shortly.
>
> Regards,
> Lucas
>
thanks for the review.

adam
> >  static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
> >       {
> >               .compatible = "fsl,imx8mm-vpu-blk-ctrl",
>
>