Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp380135pxb; Sun, 10 Oct 2021 00:08:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOmheQ+YIieYuC1LjCfSXQBea9wT2eTrNJpAo0fECDAcw7uSMWbULA0ih0cjQdD4mbVA6L X-Received: by 2002:a63:ff45:: with SMTP id s5mr12717205pgk.423.1633849708520; Sun, 10 Oct 2021 00:08:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633849708; cv=none; d=google.com; s=arc-20160816; b=hZXIWNrX4dTxwKZ5LsmopPvCr3vXpfsR69isBJ1B7b6QSFFE/B61dd/5B/8HsVi9xS SkMIUsog28FWKee9/uqWQ5cBgCjKizrGe4dtCh4T15w/u4NMPH3omcDsRcnVH/oR9F/e VgxxcxSIw70ZBy/J+MoaRgnQHSpMPhkbguGcG/NMlbGfUVDH+D1Vwb5otfxlm/8qomwJ 8wDb/zdTCKDJ8HLds+3LgilhgblB7TJ4p0lzDcIeDsN8Q3urql4d1F86n6TXWUnAPU3H nfb9dPBevbfICSXi27zb1fq3iNhKQTiZNf4H1UTyb/iSurAcjfXDGMKTNcpFb2kpaFEB Xh/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=UPKAvywdwlKeEJikpTkqHb15YKhGhSy/lSDPKUWbiCE=; b=vupMbg0bsWT7+VEBVPEDDA057K3sHwSYPIORb8Pvg0AD5moX/Ce4UvHFz0s8NO4ovr HiBn8G2Aq4C5v3PsSenFv/F2gPNNIuScTkgulJqmhb4izcdgUP+0kFvaJUD9Zv1BTT4A Bd3XzEP65uT2F7QqlJ5/v7e0Kteg6Rzk3sBOsiFiQi5ebgxeGx2LPerE7y+IfbT0J/eX q2VgyZ1RYbRYfoWpaIvVGCyewH3zY/btKik+bO9DuXg52ZUWtlRQxK4TtVfqHayQ3rqr 6oQQaAiwPOO3eq1FX+5EudxWdCss4qiYQdLm2ZLP+zhEDzNJUrKPYeQmhLCovKP9AfO8 /mHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 75si5958110pga.225.2021.10.10.00.08.16; Sun, 10 Oct 2021 00:08:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231140AbhJJHIY (ORCPT + 99 others); Sun, 10 Oct 2021 03:08:24 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:34096 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230520AbhJJHHY (ORCPT ); Sun, 10 Oct 2021 03:07:24 -0400 X-UUID: 6e5c8d03af7041b7a7b1a07beca3a2f9-20211010 X-UUID: 6e5c8d03af7041b7a7b1a07beca3a2f9-20211010 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 530102062; Sun, 10 Oct 2021 15:05:22 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Sun, 10 Oct 2021 15:05:20 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 10 Oct 2021 15:05:19 +0800 From: Kewei Xu To: CC: , , , , , , , , , , , , , , Subject: [PATCH v8 5/5] i2c: mediatek: modify bus speed calculation formula Date: Sun, 10 Oct 2021 15:05:16 +0800 Message-ID: <20211010070516.26763-6-kewei.xu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211010070516.26763-1-kewei.xu@mediatek.com> References: <20211010070516.26763-1-kewei.xu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When clock-div is 0 or greater than 1, the bus speed calculated by the old speed calculation formula will be larger than the target speed. So we update the formula. Signed-off-by: Kewei Xu Reviewed-by: Qii Wang --- drivers/i2c/busses/i2c-mt65xx.c | 35 +++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 3db4ed3f9050..ad07647f88d5 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -68,11 +68,12 @@ #define I2C_DEFAULT_CLK_DIV 5 #define MAX_SAMPLE_CNT_DIV 8 #define MAX_STEP_CNT_DIV 64 -#define MAX_CLOCK_DIV 256 +#define MAX_CLOCK_DIV_8BITS 256 +#define MAX_CLOCK_DIV_5BITS 32 #define MAX_HS_STEP_CNT_DIV 8 -#define I2C_STANDARD_MODE_BUFFER (1000 / 2) -#define I2C_FAST_MODE_BUFFER (300 / 2) -#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) +#define I2C_STANDARD_MODE_BUFFER (1000 / 3) +#define I2C_FAST_MODE_BUFFER (300 / 3) +#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) #define I2C_CONTROL_RS (0x1 << 1) #define I2C_CONTROL_DMA_EN (0x1 << 2) @@ -724,14 +725,26 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, unsigned int best_mul; unsigned int cnt_mul; int ret = -EINVAL; + int clock_div_constraint = 0; if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; + if (i2c->use_default_timing) { + clock_div_constraint = 0; + } else if (i2c->dev_comp->ltiming_adjust && + i2c->ac_timing.inter_clk_div > 1) { + clock_div_constraint = 1; + } else if (i2c->dev_comp->ltiming_adjust && + i2c->ac_timing.inter_clk_div == 0) { + clock_div_constraint = -1; + } + max_step_cnt = mtk_i2c_max_step_cnt(target_speed); base_step_cnt = max_step_cnt; /* Find the best combination */ - opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); + opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed) + + clock_div_constraint; best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; /* Search for the best pair (sample_cnt, step_cnt) with @@ -766,7 +779,8 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, sample_cnt = base_sample_cnt; step_cnt = base_step_cnt; - if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { + if ((clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint))) > + target_speed) { /* In this case, hardware can't support such * low i2c_bus_freq */ @@ -853,13 +867,16 @@ static int mtk_i2c_set_speed_adjust_timing(struct mtk_i2c *i2c, target_speed = i2c->speed_hz; parent_clk /= i2c->clk_src_div; - if (i2c->dev_comp->timing_adjust) - max_clk_div = MAX_CLOCK_DIV; + if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) + max_clk_div = MAX_CLOCK_DIV_5BITS; + else if (i2c->dev_comp->timing_adjust) + max_clk_div = MAX_CLOCK_DIV_8BITS; else max_clk_div = 1; for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { clk_src = parent_clk / clk_div; + i2c->ac_timing.inter_clk_div = clk_div - 1; if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { /* Set master code speed register */ @@ -906,8 +923,6 @@ static int mtk_i2c_set_speed_adjust_timing(struct mtk_i2c *i2c, break; } - i2c->ac_timing.inter_clk_div = clk_div - 1; - return 0; } -- 2.25.1