Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp1035335pxb; Sun, 10 Oct 2021 18:44:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxDPcJQNz02xcvb/RbPDWa3m/R+Wnz7Q6LC38soFV30lNfe50dd3sWghnlIeGI1AbbNGPH0 X-Received: by 2002:aa7:814f:0:b0:44d:626:8b96 with SMTP id d15-20020aa7814f000000b0044d06268b96mr7754692pfn.65.1633916699379; Sun, 10 Oct 2021 18:44:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633916699; cv=none; d=google.com; s=arc-20160816; b=Rsh6sWnvUl8UDu+bMwh6V3BOnIe5blJ2mcFMqrIxNDIdzMERAukIZcpkhQ9da4M/R/ KNeFVp//GEnTSwg/FJhCunjGXmoAGrxm0umB2KP7ISIIjTiXKgVUuiqdWU+K0OtDaE3/ RDONo24weg9E/BM6ty0+mG5YzSYDTehqEpl82MNEuZwnNnEIcQm/fNHthmmtnALFeWCC xBxk3JPkhLuo+4/yxs1EZuEKVGtdKBHsB+5+cPZt1YxxpYMZbVe7hjre5AoomFJarT9Y w0CFPueksyfsGuRNIauFkPYHnJt53XMdlaN6toPtF0Jo/l4EpfQv2lD9+oDh6Ogc30em Zaqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RvcgLEGbaMhvDuwWOKcUYnieM2kaNhY3qJwye4t2Aik=; b=dGSN1jIVpsAXB+7S6LwcsKRpNMtxdBf8EYp6hQCuQeJD2R743qkBHbnh2ErFPcawjG 4SXFPfQEGLxtHyOkyb7We8bMGhreobooUrJ0k9kCf5nJfLpXe+dJ4G3re6rWHs9E4KkI 8iycR4FxW0hzO/bccEnDaAHeaWTXjDI6a/NQSAhXrUetTiBYl4rldcWAFj6MlkjoHKks FGU83FAEAJK1QruuB97pL0gnmgw+X5HayNGqa0QZM2oTa/yqnswO510jOpnTIZD0VSil JkDWFpm1I3Ve/+X+DKuf4wOGOxzY2puE6ok5AJX9/MCOxtwDmdM02F3u76HmM5U8NZUT ByTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=A3bNLmkJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b16si9380750pfb.259.2021.10.10.18.44.47; Sun, 10 Oct 2021 18:44:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=A3bNLmkJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233486AbhJKBc5 (ORCPT + 99 others); Sun, 10 Oct 2021 21:32:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233386AbhJKBct (ORCPT ); Sun, 10 Oct 2021 21:32:49 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D249EC061768; Sun, 10 Oct 2021 18:30:48 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id w19so1180025edd.2; Sun, 10 Oct 2021 18:30:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RvcgLEGbaMhvDuwWOKcUYnieM2kaNhY3qJwye4t2Aik=; b=A3bNLmkJ0m/S8kPfQ3O/Gr+CtNR+SwGApWSzu0OMIf2ol5uYUDefdUM2edTmAx4pIX sNDtvTuUuYDwRMJTKLJEPFgUZFAfetWd37qPbYO1tXLT7SuCJ8AVwKTOxM8qhYhIBw9I JNQtY5cesRSOClG7uT1zyo2VZS4RoIM0LZqQm4p6h6gH8boysVrCwiqDi7kGxCPZKyRF v6ih7gfwFm+aPmYVBwgz2n8quDeqS70CwBQmDXsATFp9rJWQfjnrmUmWJd3tMdtdI+ss y++K1PMGPhBJ0lfWexRRu2fQZZ5XDCfcgFzVkxO4UBFA6kXDHZjPuc/zQ2Lmg1Q1elxX 2VRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RvcgLEGbaMhvDuwWOKcUYnieM2kaNhY3qJwye4t2Aik=; b=WVzkJswutFhTjuNydAQ2O65DaNnOT7ATBhN+0LYbGh8WjjYi7YInnbR42B1jvrsIWV ASsGP8E5jDoV9DcbP/p7xQMND1usQTE79v5Jt9AdNbk6ZbkFunXG6GvqH0u8GVxatRrR l5EAOazDGF/rd2dBTBTambtd2BP+R3SmoSuxynPb+9PiQE8mo7/pkk3wfyn3KSn2sAtY fLF7h4647F8aqlvaOisw4GnUQjM5b8jkDfXMJ1lcF6el111sr4m2pZpjahAsREAxPYUx Hq8aTvQSJWs6OrNervQCaLABVKaBstvYuecKZcmKrQtx+6eNdZce/cW0T0CUDUhwdBCN MpbA== X-Gm-Message-State: AOAM530102Mgzof7KklTKMC1HguqPQjJ755o8bLbuHVpfBJ4e6/kKRzj 7PXA68DJMLj6o6RtMKbS9Ho= X-Received: by 2002:a17:906:c0d:: with SMTP id s13mr7979501ejf.309.1633915847371; Sun, 10 Oct 2021 18:30:47 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id m15sm21314edd.5.2021.10.10.18.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 18:30:47 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith Subject: [net-next PATCH v5 05/14] drivers: net: dsa: qca8k: add support for cpu port 6 Date: Mon, 11 Oct 2021 03:30:15 +0200 Message-Id: <20211011013024.569-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211011013024.569-1-ansuelsmth@gmail.com> References: <20211011013024.569-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently CPU port is always hardcoded to port 0. This switch have 2 CPU port. The original intention of this driver seems to be use the mac06_exchange bit to swap MAC0 with MAC6 in the strange configuration where device have connected only the CPU port 6. To skip the introduction of a new binding, rework the driver to address the secondary CPU port as primary and drop any reference of hardcoded port. With configuration of mac06 exchange, just skip the definition of port0 and define the CPU port as a secondary. The driver will autoconfigure the switch to use that as the primary CPU port. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 50 +++++++++++++++++++++++++++++------------ drivers/net/dsa/qca8k.h | 2 -- 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index e335a4cfcb75..de50116d483e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -977,6 +977,22 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) return ret; } +static int qca8k_find_cpu_port(struct dsa_switch *ds) +{ + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + + /* Find the connected cpu port. Valid port are 0 or 6 */ + if (dsa_is_cpu_port(ds, 0)) + return 0; + + dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); + + if (dsa_is_cpu_port(ds, 6)) + return 6; + + return -EINVAL; +} + static int qca8k_parse_port_config(struct qca8k_priv *priv) { @@ -1011,13 +1027,14 @@ static int qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + u8 cpu_port; int ret, i; u32 mask; - /* Make sure that port 0 is the cpu port */ - if (!dsa_is_cpu_port(ds, 0)) { - dev_err(priv->dev, "port 0 is not the CPU port"); - return -EINVAL; + cpu_port = qca8k_find_cpu_port(ds); + if (cpu_port < 0) { + dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); + return cpu_port; } /* Parse CPU port config to be later used in phy_link mac_config */ @@ -1059,7 +1076,7 @@ qca8k_setup(struct dsa_switch *ds) dev_warn(priv->dev, "mib init failed"); /* Enable QCA header mode on the cpu port */ - ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), + ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port), QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); if (ret) { @@ -1081,10 +1098,10 @@ qca8k_setup(struct dsa_switch *ds) /* Forward all unknown frames to CPU port for Linux processing */ ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); + BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | + BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | + BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | + BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); if (ret) return ret; @@ -1092,7 +1109,7 @@ qca8k_setup(struct dsa_switch *ds) for (i = 0; i < QCA8K_NUM_PORTS; i++) { /* CPU port gets connected to all user ports of the switch */ if (dsa_is_cpu_port(ds, i)) { - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port), QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); if (ret) return ret; @@ -1104,7 +1121,7 @@ qca8k_setup(struct dsa_switch *ds) ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), QCA8K_PORT_LOOKUP_MEMBER, - BIT(QCA8K_CPU_PORT)); + BIT(cpu_port)); if (ret) return ret; @@ -1610,9 +1627,12 @@ static int qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int port_mask = BIT(QCA8K_CPU_PORT); + int port_mask, cpu_port; int i, ret; + cpu_port = dsa_to_port(ds, port)->cpu_dp->index; + port_mask = BIT(cpu_port); + for (i = 1; i < QCA8K_NUM_PORTS; i++) { if (dsa_to_port(ds, i)->bridge_dev != br) continue; @@ -1639,7 +1659,9 @@ static void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int i; + int cpu_port, i; + + cpu_port = dsa_to_port(ds, port)->cpu_dp->index; for (i = 1; i < QCA8K_NUM_PORTS; i++) { if (dsa_to_port(ds, i)->bridge_dev != br) @@ -1656,7 +1678,7 @@ qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) * this port */ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT)); + QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); } static int diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index bc9c89dd7e71..781521e6a965 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -24,8 +24,6 @@ #define QCA8K_NUM_FDB_RECORDS 2048 -#define QCA8K_CPU_PORT 0 - #define QCA8K_PORT_VID_DEF 1 /* Global control registers */ -- 2.32.0