Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp1153181pxb; Sun, 10 Oct 2021 22:39:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHeKTXbjurXvnQqF9QYAfRIEHaFTa1vFHVRPmaENnlVicCBhWGg9mUBoH8GR1kSz0/iapI X-Received: by 2002:a17:90a:51:: with SMTP id 17mr27752268pjb.185.1633930750095; Sun, 10 Oct 2021 22:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633930750; cv=none; d=google.com; s=arc-20160816; b=YI2g6CvTMufFfrIOskRZr2BnqqwHdpozKqsjok8mBOu/j6fHtQqpSbh1Ib8aEGqYaw 8Ie4enfg0QQZ5ARahxajr++qNTSbNhTT1OkpkPwQxpsPYi3aq5BVek2X/qHcN+dPrLeP g3waIekOm2t0yTvt2bDGBmjDDY3zulhnw//255npWLyazdQtJWmSY/b1dqQcV7ABxc0w pZraQvoY0d0rxWbI9VixGo9whMxesSAwafWuhNly5z0+xVz50eE1+CPl/tRbzt0xyX8+ WTuUM3u9URTNtTb/a2+JVGWLgENPhXaeeSzEgDy0QqjcF41W3BpC7wJ5Y2CGfz48h8+C IQKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=rhpX1SIh+W3Ko252kloPAiI8lqIsB+od8mLRg3LOsMw=; b=a9nz3vCAZl2iEDtrynbiUH9tno2niaiyJdloY/ryADziLmGVPkjgDYjYaLeKb8Zu+l X5QxcyX+32donQ6ilxrTPsm360KWWS9uF3/BjBq+O18penT0sohOvdyMSFmdrLeE44Cv EkHltfX5cyESrWuOxZdctNeHXezkg0rIViMAQBmAxMjHaXPt7lXC0U8kciurZUiTVB8j spVleExw6LQe27MM2GbZ68c8SblNJXp1G16plT70akFjvA9RRbwxoBdaOdL6AbaGztBh 9kMQXkj2Lk1J8lYQs7kI2FzZsuezP171AfmoSuyHv76vobRrEpCo7FRMBUkB+mN/ZCof 3uEA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=puri.sm Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q2si12144370pfj.327.2021.10.10.22.38.58; Sun, 10 Oct 2021 22:39:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=puri.sm Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233902AbhJKDei convert rfc822-to-8bit (ORCPT + 99 others); Sun, 10 Oct 2021 23:34:38 -0400 Received: from comms.puri.sm ([159.203.221.185]:32822 "EHLO comms.puri.sm" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233264AbhJKDeh (ORCPT ); Sun, 10 Oct 2021 23:34:37 -0400 Received: from localhost (localhost [127.0.0.1]) by comms.puri.sm (Postfix) with ESMTP id 4426CE01C9; Sun, 10 Oct 2021 20:32:37 -0700 (PDT) Received: from comms.puri.sm ([127.0.0.1]) by localhost (comms.puri.sm [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0Vpvc_Y5b0Jg; Sun, 10 Oct 2021 20:32:36 -0700 (PDT) From: Sebastian Krzyszkowiak To: Sebastian Reichel , linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Dirk Brandewie , kernel@puri.sm, stable@vger.kernel.org Subject: Re: [PATCH v2 1/2] power: supply: max17042_battery: Clear status bits in interrupt handler Date: Mon, 11 Oct 2021 05:32:30 +0200 Message-ID: <11303414.9r73sBlGM0@pliszka> In-Reply-To: <20210914121806.1301131-1-sebastian.krzyszkowiak@puri.sm> References: <20210914121806.1301131-1-sebastian.krzyszkowiak@puri.sm> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On wtorek, 14 wrzeĊ›nia 2021 14:18:05 CEST Sebastian Krzyszkowiak wrote: > The gauge requires us to clear the status bits manually for some alerts > to be properly dismissed. Previously the IRQ was configured to react only > on falling edge, which wasn't technically correct (the ALRT line is active > low), but it had a happy side-effect of preventing interrupt storms > on uncleared alerts from happening. > > Fixes: 7fbf6b731bca ("power: supply: max17042: Do not enforce (incorrect) > interrupt trigger type") Cc: > Signed-off-by: Sebastian Krzyszkowiak > --- > v2: added a comment on why it clears all alert bits > --- > drivers/power/supply/max17042_battery.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/power/supply/max17042_battery.c > b/drivers/power/supply/max17042_battery.c index 8dffae76b6a3..da78ffe6a3ec > 100644 > --- a/drivers/power/supply/max17042_battery.c > +++ b/drivers/power/supply/max17042_battery.c > @@ -876,6 +876,10 @@ static irqreturn_t max17042_thread_handler(int id, void > *dev) max17042_set_soc_threshold(chip, 1); > } > > + /* we implicitly handle all alerts via power_supply_changed */ > + regmap_clear_bits(chip->regmap, MAX17042_STATUS, > + 0xFFFF & ~(STATUS_POR_BIT | STATUS_BST_BIT)); > + > power_supply_changed(chip->battery); > return IRQ_HANDLED; > } Ping? Seems this didn't get applied yet. S.