Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp1612039pxb; Mon, 11 Oct 2021 09:28:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwrMU0BlFudpQC8FECOU0A5zz4cT8OvUc8UapMhfnV2pHDG4HcQnWFAiW5eRi2VAyzzazeb X-Received: by 2002:a17:907:1199:: with SMTP id uz25mr26490283ejb.470.1633969694442; Mon, 11 Oct 2021 09:28:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633969694; cv=none; d=google.com; s=arc-20160816; b=wr9vKpoHd0AKz6M9tW6PWL9SsLtjF07UZvM0CzNtO/xvwFefgA77jSYTTXNG/ijfbM PB/TuywhE6v5TbSYzKVo8Dp3N/3ANstZ0lPDPn5Kx5f08W0vZC+OUtThPfc4z1RQntUi mC8pjqUuAF0DSzsjGcZeMSK1YpuwWUlHjGkzOU+wytf6ycrrgBdjkgEz4rBH/Br8sGRl +Y7upYib9SGDnG/RWDerTq0mE0Opq2jxWt7uoWkVok2HzWcOZ3plUTzm0HuacTkhFgP9 x6oUGlS99utkUfh2OMkSM4yqgtbsNlcEMRoUIJ1k+5ySjXKrRVFgDYZ50EKGqZY60/8X O2RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LHDrSUduZMqe+KE7X3sqH8cjc1WeEiyFCBz+ZNtU2dU=; b=b9InUBUUGzqDkIvUGQyL6GQPjhoXQ3I0Mz7IOCla6teOMxQN6dXL59ifzl9or1vNSk 562n3SH5qyHAAzm7nPjqylosrk252/NuapaaEsDAD07qvknt/UGT2OMb7US/pJp6Gjgr gTJ3HlHGX2bcr+3WXH9gFIkO7UYEWhBq9CqUEBpxcd2UWvnfEA8i+gkai2Ltw+5kJUgo hOn0FpkRG3zgbnMA+V2SO3iLCDvTJXwDeqsHqzxCgxOb/8dtMCMxJJGU2lCby5YTNXMZ vwzztFDzdbLSrfE0S3f3Wc9d8UrKkV8Cxn9UEod4R6/CFvs+F0bp2BgqJBdT6a/Q2hGE v5Ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Y8cUKprr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bh21si12841539ejb.428.2021.10.11.09.27.50; Mon, 11 Oct 2021 09:28:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Y8cUKprr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236888AbhJKN06 (ORCPT + 99 others); Mon, 11 Oct 2021 09:26:58 -0400 Received: from mail.kernel.org ([198.145.29.99]:53772 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236854AbhJKN05 (ORCPT ); Mon, 11 Oct 2021 09:26:57 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9F9E460F35; Mon, 11 Oct 2021 13:24:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1633958697; bh=LEZbhktiDsSW+AwzStPDh+VwFomRdqomqsmfTAm2/aY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y8cUKprreXse2sf+Od1xtI2PwfWHJEK1o0LhxjXvuXjvtKARsNBuXxxJzowHNZh9I 2AKJ1iEMrNNbky/N5gmhCqdWeesxYR4OzP2LMF7JSTYPVy2oqSjx92arAgil2QBZTX b+4UFaSi207sdMjcsVAvxcTZOEv4/QLC8kM/+T0oJqjPr14yCryQgQpx8e0JpHS+oc QjW5U2Tnrd9MOwGz4/8RvcpncnjpOEmGsBwVDR/K4CrfiuwhhVHCJGuWhsslCEI6dY t0zaEzkhF5lHCU3PUpJ4DFtHfwxb+oBeQnYk1xb+BYfDBY1xkFDxDRY26EvwLPjb21 jHM2gP0IQZRgw== From: guoren@kernel.org To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Rob Herring , Palmer Dabbelt Subject: [PATCH 2/2] dt-bindings: update riscv plic claim-mask-support property Date: Mon, 11 Oct 2021 21:24:31 +0800 Message-Id: <20211011132431.2792797-2-guoren@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011132431.2792797-1-guoren@kernel.org> References: <20211011132431.2792797-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren Add claim-mask-support to control riscv,plic don't call unnecessary mask/unmask operations. Signed-off-by: Guo Ren Cc: Rob Herring Cc: Palmer Dabbelt Cc: Anup Patel Cc: Atish Patra --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 08d5a57ce00f..f32c1792604c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -71,6 +71,8 @@ properties: description: Specifies how many external interrupts are supported by this controller. + claim-mask-support: true + required: - compatible - '#address-cells' -- 2.25.1