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[23.128.96.18]) by mx.google.com with ESMTP id a20si13287303ejx.753.2021.10.11.18.02.39; Mon, 11 Oct 2021 18:03:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20210112.gappssmtp.com header.s=20210112 header.b=UEKN7SJX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230074AbhJLA7W (ORCPT + 99 others); Mon, 11 Oct 2021 20:59:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230172AbhJLA7V (ORCPT ); Mon, 11 Oct 2021 20:59:21 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C796C06161C for ; Mon, 11 Oct 2021 17:57:20 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id y3so28399439wrl.1 for ; Mon, 11 Oct 2021 17:57:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=HrgUn3DKWZ7MmEFAtfrRtljQYBgKoJersDhT1IC80/A=; b=UEKN7SJXViOLIpLUXMBH07yr+kRk8wq5gTyFGoRE9r/FfKxtpz90BaWEbcHVPJTR+Y w3CJ9ax6XuCP17QkvRiHebrKOWNpsE6iP52Rhpg0RR3WkVxEg1M0jg15XvxKDUHcIbur e8keyInu70XI7fBsNIbfwYeDeCAXSUjjdc+x1oBfqO9tGNVoundVn061eSZ8eXdX2CNH NVLTH6b0Q9FknSZwTJkUnMY9RS6nobK5nSvBdOMnEQxtLWZl3N30Aplx64MB5xu5Yllt ExVR+pq5IzSAyx8UrIKM6vymfK6gKs5RMfClfn0HIQFJqfpHva/9F/pW/k1MGliyTYm7 F3Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=HrgUn3DKWZ7MmEFAtfrRtljQYBgKoJersDhT1IC80/A=; b=Sf1GOGNXzpwUoc2fc3ge43m7GMC+Vb0OVT4TtNYlI2D8OGvkccqRVFiv7takrlEduv RxcrjnAqm6nQoRoWYIFdJ7DkzlhyRoXw6QlIuLgL9ryWTRGC4vJou9hkWRcCnc5xlrNU qfr9jfVJE+ewS1bCPmKRTgmHWDz1xx6ov54wP0+6X6btjlMeZKVzTeAfYC7UnJC73HI1 gPN/EqSIaOxdN+krFcrXXvAXfkdyNJPwcIHiUJViT+0GmYvADFvpM1vdv+O3H5Vdqey5 kXbi8WSx4EEMOfi4EuV9MJwRcGKKlY3rEQfWkqtc02ZLwhcIUpYprbC0c0P/2QdCNtVD nOyg== X-Gm-Message-State: AOAM532/xqnkQaHFzKt7sFwy1e8oSlNaAC+27jxr2oTDJFNSp+bPau9E eOPDhQLR6SXBieEDsO5DRoKG6DuSfSQbiO57MD4Upw== X-Received: by 2002:a7b:c742:: with SMTP id w2mr2508708wmk.61.1634000239044; Mon, 11 Oct 2021 17:57:19 -0700 (PDT) MIME-Version: 1.0 References: <20211011081820.1135261-1-anup.patel@wdc.com> <20211011081820.1135261-2-anup.patel@wdc.com> <4300884.9bbH7Ay9ha@diego> In-Reply-To: <4300884.9bbH7Ay9ha@diego> From: Anup Patel Date: Tue, 12 Oct 2021 06:27:07 +0530 Message-ID: Subject: Re: [PATCH v8 1/8] RISC-V: Enable CPU_IDLE drivers To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring , linux-riscv , Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , DTML , "linux-kernel@vger.kernel.org List" , "open list:THERMAL" , linux-arm-kernel , Anup Patel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 12, 2021 at 4:46 AM Heiko St=C3=BCbner wrote: > > Hi Anup, > > Am Montag, 11. Oktober 2021, 10:18:13 CEST schrieb Anup Patel: > > We force select CPU_PM and provide asm/cpuidle.h so that we can > > use CPU IDLE drivers for Linux RISC-V kernel. > > > > Signed-off-by: Anup Patel > > --- > > arch/riscv/Kconfig | 7 +++++++ > > arch/riscv/configs/defconfig | 1 + > > arch/riscv/configs/rv32_defconfig | 1 + > > arch/riscv/include/asm/cpuidle.h | 24 ++++++++++++++++++++++++ > > arch/riscv/kernel/process.c | 3 ++- > > 5 files changed, 35 insertions(+), 1 deletion(-) > > create mode 100644 arch/riscv/include/asm/cpuidle.h > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 8de2afb460f7..d02f1f5a2431 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -46,6 +46,7 @@ config RISCV > > select CLONE_BACKWARDS > > select CLINT_TIMER if !MMU > > select COMMON_CLK > > + select CPU_PM if CPU_IDLE > > select EDAC_SUPPORT > > select GENERIC_ARCH_TOPOLOGY if SMP > > select GENERIC_ATOMIC64 if !64BIT > > @@ -564,5 +565,11 @@ source "kernel/power/Kconfig" > > > > endmenu > > > > +menu "CPU Power Management" > > + > > +source "drivers/cpuidle/Kconfig" > > + > > +endmenu > > + > > source "arch/riscv/kvm/Kconfig" > > source "drivers/firmware/Kconfig" > > another issue, the "arch/riscv/kvm/Kconfig" line above comes from a > commit that is not in the riscv-tree at all but in the kvm-tree [0], > making this patch fail to apply onto riscv/for-next alone. > > If you have multiple independent patch series in flight, like shown in > the github branch you references, it might be easier to base each on > top of the relevant branch cleanly and after one gets applied rebase > the other ones. I know I have been doing that but this time accidently picked the wrong branch to rebase upon. Thanks for trying. Regards, Anup > > That way you're not dependent on the others going in first and also > people can test patch series individually without too much hassle. > > Thanks > Heiko > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git/com= mit/?h=3Dnext&id=3D99cdc6c18c2d815e940e81b9b477d469bdd41788 > >