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From:   Bharat Bhushan <bbhushan2@marvell.com>
To:     Bharat Bhushan <bbhushan2@marvell.com>,
        "will@kernel.org" <will@kernel.org>,
        "mark.rutland@arm.com" <mark.rutland@arm.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Bhaskara Budiredla <bbudiredla@marvell.com>
Subject: RE: [PATCH v4 4/4] perf/marvell: cn10k DDR perf event core ownership
Thread-Topic: [PATCH v4 4/4] perf/marvell: cn10k DDR perf event core ownership
Thread-Index: AQHXrd2Xcorcgtmsy0+X5+eU/Myu66vPIx5w
Date:   Tue, 12 Oct 2021 08:02:10 +0000
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References: <20210920050823.10853-1-bbhushan2@marvell.com>
 <20210920050823.10853-5-bbhushan2@marvell.com>
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Adding Bhaskara

> -----Original Message-----
> From: Bharat Bhushan <bbhushan2@marvell.com>
> Sent: Monday, September 20, 2021 10:38 AM
> To: will@kernel.org; mark.rutland@arm.com; robh+dt@kernel.org; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Cc: Bharat Bhushan <bbhushan2@marvell.com>
> Subject: [PATCH v4 4/4] perf/marvell: cn10k DDR perf event core ownership
>=20
> As DDR perf event counters are not per core, so they should be accessed o=
nly by
> one core at a time. Select new core when previously owning core is going =
offline.
>=20
> Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
> ---
> v1->v2->v3->v4:
>  - No change
>=20
>  drivers/perf/marvell_cn10k_ddr_pmu.c | 50 ++++++++++++++++++++++++++--
>  include/linux/cpuhotplug.h           |  1 +
>  2 files changed, 49 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c
> b/drivers/perf/marvell_cn10k_ddr_pmu.c
> index 21fccb9090c5..bef0cee3a46a 100644
> --- a/drivers/perf/marvell_cn10k_ddr_pmu.c
> +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
> @@ -129,6 +129,7 @@ struct cn10k_ddr_pmu {
>  	int active_events;
>  	struct perf_event *events[DDRC_PERF_NUM_COUNTERS];
>  	struct hrtimer hrtimer;
> +	struct hlist_node node;
>  };
>=20
>  #define to_cn10k_ddr_pmu(p)	container_of(p, struct cn10k_ddr_pmu, pmu)
> @@ -610,6 +611,24 @@ static enum hrtimer_restart
> cn10k_ddr_pmu_timer_handler(struct hrtimer *hrtimer)
>  	return HRTIMER_RESTART;
>  }
>=20
> +static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu, struct
> +hlist_node *node) {
> +	struct cn10k_ddr_pmu *pmu =3D hlist_entry_safe(node, struct
> cn10k_ddr_pmu,
> +						     node);
> +	unsigned int target;
> +
> +	if (cpu !=3D pmu->cpu)
> +		return 0;
> +
> +	target =3D cpumask_any_but(cpu_online_mask, cpu);
> +	if (target >=3D nr_cpu_ids)
> +		return 0;
> +
> +	perf_pmu_migrate_context(&pmu->pmu, cpu, target);
> +	pmu->cpu =3D target;
> +	return 0;
> +}
> +
>  static int cn10k_ddr_perf_probe(struct platform_device *pdev)  {
>  	struct cn10k_ddr_pmu *ddr_pmu;
> @@ -661,18 +680,31 @@ static int cn10k_ddr_perf_probe(struct
> platform_device *pdev)
>  	hrtimer_init(&ddr_pmu->hrtimer, CLOCK_MONOTONIC,
> HRTIMER_MODE_REL);
>  	ddr_pmu->hrtimer.function =3D cn10k_ddr_pmu_timer_handler;
>=20
> +	cpuhp_state_add_instance_nocalls(
> +
> 	CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
> +				&ddr_pmu->node);
> +
>  	ret =3D perf_pmu_register(&ddr_pmu->pmu, name, -1);
>  	if (ret)
> -		return ret;
> +		goto error;
>=20
>  	pr_info("CN10K DDR PMU Driver for ddrc@%llx\n", res->start);
>  	return 0;
> +error:
> +	cpuhp_state_remove_instance_nocalls(
> +
> 	CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
> +				&ddr_pmu->node);
> +	return ret;
>  }
>=20
>  static int cn10k_ddr_perf_remove(struct platform_device *pdev)  {
>  	struct cn10k_ddr_pmu *ddr_pmu =3D platform_get_drvdata(pdev);
>=20
> +	cpuhp_state_remove_instance_nocalls(
> +
> 	CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
> +				&ddr_pmu->node);
> +
>  	perf_pmu_unregister(&ddr_pmu->pmu);
>  	return 0;
>  }
> @@ -695,12 +727,26 @@ static struct platform_driver cn10k_ddr_pmu_driver =
=3D {
>=20
>  static int __init cn10k_ddr_pmu_init(void)  {
> -	return platform_driver_register(&cn10k_ddr_pmu_driver);
> +	int ret;
> +
> +	ret =3D cpuhp_setup_state_multi(
> +
> 	CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
> +				"perf/marvell/cn10k/ddr:online", NULL,
> +				cn10k_ddr_pmu_offline_cpu);
> +	if (ret)
> +		return ret;
> +
> +	ret =3D platform_driver_register(&cn10k_ddr_pmu_driver);
> +	if (ret)
> +		cpuhp_remove_multi_state(
> +
> 	CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE);
> +	return ret;
>  }
>=20
>  static void __exit cn10k_ddr_pmu_exit(void)  {
>  	platform_driver_unregister(&cn10k_ddr_pmu_driver);
> +
> 	cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_MARVELL_CN10K_D
> DR_ONLINE);
>  }
>=20
>  module_init(cn10k_ddr_pmu_init);
> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h inde=
x
> 832d8a74fa59..a4b521f12b58 100644
> --- a/include/linux/cpuhotplug.h
> +++ b/include/linux/cpuhotplug.h
> @@ -227,6 +227,7 @@ enum cpuhp_state {
>  	CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,
>  	CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
>  	CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE,
> +	CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
>  	CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
>  	CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
>  	CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
> --
> 2.17.1