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From:   "Tian, Kevin" <kevin.tian@intel.com>
To:     "hch@lst.de" <hch@lst.de>
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Subject: RE: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO
Thread-Topic: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO
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> From: hch@lst.de <hch@lst.de>
> Sent: Thursday, October 14, 2021 4:22 PM
>=20
> > > > What I don't really understand is why ARM, with an IOMMU that
> supports
> > > > PTE WB, has devices where dev_is_dma_coherent() =3D=3D false ?
> > >
> > > Because no IOMMU in the world can help that fact that a periphal on t=
he
> > > SOC is not part of the cache coherency protocol.
> >
> > but since DMA goes through IOMMU then isn't IOMMU the one who
> > should decide the final cache coherency? What would be the case
> > if the IOMMU sets WB while the peripheral doesn't want it?
>=20
> No.  And IOMMU deal with address translation, it can't paper over
> a fact that there is no coherency possible.

Does it relate to the ATS story where the device gets translated address
from IOMMU and then directly sends request to memory controller?
In this way if the device is not in cache coherency domain then nothing
can change it.

Then if ATS is disabled, suppose the untranslated request from the
device is translated and forwarded by IOMMU to the memory controller.
In this case IOMMU should be able to join the coherency protocol
even when the originating device itself cannot.

Is above understanding correct?

Thanks
Kevin