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Miller" , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Rob Herring , Shawn Guo , Andrew Lunn , Heiner Kallweit , Russell King , Vivien Didelot , Vladimir Oltean , Florian Fainelli , Prasanna Vengateshan , Ansuel Smith , =?Windows-1252?Q?Alvin_=8Aipraga?= Subject: Re: [PATCH net-next 6/6] net: dsa: sja1105: parse {rx,tx}-internal-delay-ps properties for RGMII delays Thread-Topic: [PATCH net-next 6/6] net: dsa: sja1105: parse {rx,tx}-internal-delay-ps properties for RGMII delays Thread-Index: AQHXwIEVq1/AgHYHDEKe3jQ+7QpyaqvRosgAgADCSAA= Date: Thu, 14 Oct 2021 12:00:11 +0000 Message-ID: <20211014120010.im3bvg6ga7i2423n@skbuf> References: <20211013222313.3767605-1-vladimir.oltean@nxp.com> <20211013222313.3767605-7-vladimir.oltean@nxp.com> <20211013172448.2db3b99b@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> In-Reply-To: <20211013172448.2db3b99b@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; 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charset="Windows-1252" Content-ID: <28CAFDAF059A324692B703DDBA1DB6F6@eurprd04.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e9f4fc6a-d34c-44e4-a7be-08d98f0a2cc0 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2021 12:00:11.1305 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: a2RRF74/ve1k8B0H0VHgirv3v2KCIww8TbPPqheviAFUOvv+5ap063hO/hfS9mdA6i8UyhpmYGFjdu1tMgCHqA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4814 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 13, 2021 at 05:24:48PM -0700, Jakub Kicinski wrote: > Some take it or leave it comments, checkpatch pointed out some extra > brackets so I had a look at the patch. >=20 > On Thu, 14 Oct 2021 01:23:13 +0300 Vladimir Oltean wrote: > > + int rx_delay =3D -1, tx_delay =3D -1; > > =20 > > + if (!phy_interface_mode_is_rgmii(phy_mode)) > > + return 0; > > =20 > > + of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); > > + of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); >=20 > If I'm reading this right you're depending on delays being left as -1 > in case the property reads fail. Is this commonly accepted practice? It works. > Why not code it up as: >=20 > u32 rx_delay; >=20 > if (of_property_read_u32(...)) > rx_delay =3D 0; > else if (rx_delay !=3D clamp(rx_delay, ...MIN, ...MAX) > goto err; >=20 > or some such? "or some such" is not functionally equivalent. This is what would be functionally equivalent, and following your suggestion to check the return code of of_property_read_u32 instead of assigning default values, and to use clamp() instead of open-coding the bounds checks. static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int por= t, struct device_node *port_dn) { phy_interface_t phy_mode =3D priv->phy_mode[port]; struct device *dev =3D &priv->spidev->dev; int rx_delay, tx_delay; int err_rx, err_tx; if (!phy_interface_mode_is_rgmii(phy_mode)) return 0; err_rx =3D of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay= ); if (err_rx) rx_delay =3D 0; err_tx =3D of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay= ); if (err_tx) tx_delay =3D 0; if (err_rx && err_tx) { if (priv->fixed_link[port]) { dev_warn(dev, "Port %d interpreting RGMII delay settings based on \"phy-mode\" prope= rty, " "please update device tree to specify \"rx-internal-delay-ps\" and " "\"tx-internal-delay-ps\"", port); if (phy_mode =3D=3D PHY_INTERFACE_MODE_RGMII_RXID || phy_mode =3D=3D PHY_INTERFACE_MODE_RGMII_ID) rx_delay =3D 2000; if (phy_mode =3D=3D PHY_INTERFACE_MODE_RGMII_TXID || phy_mode =3D=3D PHY_INTERFACE_MODE_RGMII_ID) tx_delay =3D 2000; } } else { if ((rx_delay && rx_delay !=3D clamp(rx_delay, SJA1105_RGMII_DELAY_MIN_PS= , SJA1105_RGMII_DELAY_MAX_PS)) || (tx_delay && tx_delay !=3D clamp(tx_delay, SJA1105_RGMII_DELAY_MIN_PS= , SJA1105_RGMII_DELAY_MAX_PS))) { dev_err(dev, "port %d RGMII delay values out of range, must be between %d and %d ps\= n", port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS); return -ERANGE; } } priv->rgmii_rx_delay_ps[port] =3D rx_delay; priv->rgmii_tx_delay_ps[port] =3D tx_delay; return 0; } >=20 > > + if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) || > > + (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) || > > + (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) || > > + (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) { >=20 > nit: checkpatch says the brackets around the latter two are unnecessary, > just in case it's not for symmetry / on purpose It is on purpose.=