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Date:   Thu, 14 Oct 2021 17:43:14 +0300
From:   Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
To:     Borislav Petkov <bp@alien8.de>
Cc:     Ser Olmy <ser.olmy@protonmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>,
        "H. Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [regression] commit d298b03506d3 ("x86/fpu: Restore the masking
 out of reserved MXCSR bits")
Message-ID: <YWhCAqDxAuTh1YwE@intel.com>
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 <YWg+O1AXrWLO3Sf9@zn.tnic>
 <YWg/5h3OcQKE94Nz@intel.com>
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On Thu, Oct 14, 2021 at 05:34:14PM +0300, Ville Syrj?l? wrote:
> On Thu, Oct 14, 2021 at 04:27:07PM +0200, Borislav Petkov wrote:
> > On Thu, Oct 14, 2021 at 02:44:33PM +0300, Ville Syrj?l? wrote:
> > > I have a 32bit installation here that stopped working. Bisected it
> > > to commit d298b03506d3 ("x86/fpu: Restore the masking out of reserved
> > > MXCSR bits").
> > 
> > Lemme make sure I understand this correctly: this patch is bad and with
> > it reverted it works?
> 
> Yes.
> 
> >
> > Because before this patch, the restoring would be a more restrictive
> > than before and this patch reverts the code to the old behavior for
> > invalid MXCSR bits.

Yeah, it's a bit weird.

Hmm. Actually I just stared at the code a bit more it looks
a bit funny. Was it supposed to do this instead?

- fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask;
+ fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;

-- 
Ville Syrj?l?
Intel