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From:   Xiongfeng Wang <wangxiongfeng2@huawei.com>
To:     <mark.rutland@arm.com>, <catalin.marinas@arm.com>,
        <will@kernel.org>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <moyufeng@huawei.com>,
        <wangxiongfeng2@huawei.com>
Subject: [RFC PATCH v2] arm64: barrier: add macro dgh() to control memory accesses merging
Date:   Fri, 15 Oct 2021 17:05:11 +0800
Message-ID: <20211015090511.92421-1-wangxiongfeng2@huawei.com>
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DGH (Data Gathering Hint) prohibits merging memory accesses with
Normal-NC or Device-GRE attributes before the hint instruction with any
memory accesses appearing after the hint instruction. It can be used for
performance benefit to prevent the prior access waiting too long just to
be merged. This patch provide a macro to expose it to the arch code.

Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com>
Signed-off-by: Yufeng Mo <moyufeng@huawei.com>

---
v1->v2:
    extract this single patch from the origin patchset.
    remove the macro in the assemble code.
    add comments for macro dgh().
    modify the commit message a little bit.
---
 arch/arm64/include/asm/barrier.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 451e11e5fd23..d71a7457d619 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -18,6 +18,14 @@
 #define wfe()		asm volatile("wfe" : : : "memory")
 #define wfi()		asm volatile("wfi" : : : "memory")
 
+/*
+ * Data Gathering Hint:
+ * This instruction prohibits merging memory accesses with Normal-NC or
+ * Device-GRE attributes before the hint instruction with any memory accesses
+ * appearing after the hint instruction.
+ */
+#define dgh()		asm volatile("hint #6" : : : "memory")
+
 #define isb()		asm volatile("isb" : : : "memory")
 #define dmb(opt)	asm volatile("dmb " #opt : : : "memory")
 #define dsb(opt)	asm volatile("dsb " #opt : : : "memory")
-- 
2.20.1