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[131.111.5.141]) by smtp.gmail.com with ESMTPSA id l17sm4739706wrx.24.2021.10.15.05.15.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Oct 2021 05:15:29 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT From: Jessica Clarke In-Reply-To: <49af3dc8-0d1e-e82f-6df2-2bf8338acd3a@canonical.com> Date: Fri, 15 Oct 2021 13:15:28 +0100 Cc: Bin Meng , Daniel Lezcano , Thomas Gleixner , Guo Ren , Xiang W , Samuel Holland , Atish Patra , Rob Herring , Palmer Dabbelt , Paul Walmsley , Anup Patel , linux-kernel , devicetree , linux-riscv , OpenSBI Content-Transfer-Encoding: quoted-printable Message-Id: References: <20211015100941.17621-1-heinrich.schuchardt@canonical.com> <49af3dc8-0d1e-e82f-6df2-2bf8338acd3a@canonical.com> To: Heinrich Schuchardt X-Mailer: Apple Mail (2.3654.120.0.1.13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15 Oct 2021, at 12:54, Heinrich Schuchardt = wrote: >=20 > On 10/15/21 12:14, Bin Meng wrote: >> On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt >> wrote: >>>=20 >>> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio = access to >>> the MTIMER device. The current schema does not allow to specify = this. >>>=20 >>> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to = indicate the >>> restriction. Samuael Holland suggested in >>> lib: utils/timer: Use standard property to specify 32-bit I/O >>> = https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59f= f30008e >>> to use "reg-io-width =3D <4>;" as the reg-io-width property is = generally used >>> in the devicetree schema for such a condition. >>>=20 >>> A release candidate of the ACLINT specification is available at >>> https://github.com/riscv/riscv-aclint/releases >>>=20 >>> Add reg-io-width as optional property to the SiFive Core Local = Interruptor. >>>=20 >>> Signed-off-by: Heinrich Schuchardt = >>> --- >>> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 = +++++++ >>> 1 file changed, 7 insertions(+) >>>=20 >>> diff --git = a/Documentation/devicetree/bindings/timer/sifive,clint.yaml = b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> index a35952f48742..266012d887b5 100644 >>> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> @@ -41,6 +41,13 @@ properties: >>> reg: >>> maxItems: 1 >>>=20 >>> + reg-io-width: >>> + description: | >>> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only = support >>> + 32bit access for MTIMER. >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + const: 4 >> But this is not a "sifive,clint" anyway. Should there be a new >> dt-bindings for T-Head clint variant? >=20 > I assume by new dt-bindings variant you mean: Add a new compatible = string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. >=20 > The vendor Debian image uses: > compatible =3D "{allwinner,sun20i-d1-clint", "sifive,clint0=E2=80=9D}; I assume Bin means to stop calling it a sifive,clint0 and instead have something like "allwinner,sun20i-d1-clint", "thead,clint0" as is being done for their non-conforming PLIC. It=E2=80=99s worth = pointing out that the same is true here; the SiFive CLINT supports 64-bit accesses on RV64, so this is not compatible with a SiFive CLINT. Moreover, the RISC-V spec was clearly written in a way that intended 64-bit accesses to be supported for RV64, though was not completely explicit about that, which has now been resolved (see https://github.com/riscv/riscv-isa-manual/issues/639), so this CLINT violates the obvious intent of the pre-1.12 privileged specs (see Andrew=E2=80=99s message in the issue, which agrees with my reading). Jess