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From:   Chris Packham <chris.packham@alliedtelesis.co.nz>
To:     andrew@lunn.ch, gregory.clement@bootlin.com,
        sebastian.hesselbarth@gmail.com, robh+dt@kernel.org
Cc:     linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: [PATCH v2 2/2] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree
Date:   Mon, 18 Oct 2021 14:12:11 +1300
Message-Id: <20211018011211.3836590-3-chris.packham@alliedtelesis.co.nz>
In-Reply-To: <20211018011211.3836590-1-chris.packham@alliedtelesis.co.nz>
References: <20211018011211.3836590-1-chris.packham@alliedtelesis.co.nz>
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The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add
the necessary dts nodes and properties for this.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
This is based on the Marvell SDK. I've re-ordered the port entries to
be in ascending order renamed the wan ports and connected the SFP+.

Changes in v2:
- Remove unused port0
- Label all ports "pN"
- Add interrupt connections
- Add SFP

 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 129 ++++++++++++++++++++
 1 file changed, 129 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boo=
t/dts/marvell/cn9130-crb.dtsi
index 0885c6339d1b..d600422afd6c 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -73,6 +73,16 @@ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
 		enable-active-high;
 		regulator-always-on;
 	};
+
+	sfp: sfp {
+		compatible =3D "sff,sfp";
+		i2c-bus =3D <&cp0_i2c1>;
+		mod-def0-gpios =3D <&expander0 3 GPIO_ACTIVE_LOW>;
+		los-gpio =3D <&expander0 15 GPIO_ACTIVE_HIGH>;
+		tx-disable-gpio =3D <&expander0 2 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio =3D <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
+		status =3D "okay";
+	};
 };
=20
 &uart0 {
@@ -195,6 +205,125 @@ &cp0_mdio {
 	phy0: ethernet-phy@0 {
 		reg =3D <0>;
 	};
+
+	switch6: switch0@6 {
+		/* Actual device is MV88E6393X */
+		compatible =3D "marvell,mv88e6190";
+		#address-cells =3D <1>;
+		#size-cells =3D <0>;
+		reg =3D <6>;
+		interrupt-parent =3D <&cp0_gpio1>;
+		interrupts =3D <28 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells =3D <2>;
+
+		dsa,member =3D <0 0>;
+
+		ports {
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+
+			port@1 {
+				reg =3D <1>;
+				label =3D "p1";
+				phy-handle =3D <&switch0phy1>;
+			};
+
+			port@2 {
+				reg =3D <2>;
+				label =3D "p2";
+				phy-handle =3D <&switch0phy2>;
+			};
+
+			port@3 {
+				reg =3D <3>;
+				label =3D "p3";
+				phy-handle =3D <&switch0phy3>;
+			};
+
+			port@4 {
+				reg =3D <4>;
+				label =3D "p4";
+				phy-handle =3D <&switch0phy4>;
+			};
+
+			port@5 {
+				reg =3D <5>;
+				label =3D "p5";
+				phy-handle =3D <&switch0phy5>;
+			};
+
+			port@6 {
+				reg =3D <6>;
+				label =3D "p6";
+				phy-handle =3D <&switch0phy6>;
+			};
+
+			port@7 {
+				reg =3D <7>;
+				label =3D "p7";
+				phy-handle =3D <&switch0phy7>;
+			};
+
+			port@8 {
+				reg =3D <8>;
+				label =3D "p8";
+				phy-handle =3D <&switch0phy8>;
+			};
+
+			port@9 {
+				reg =3D <9>;
+				label =3D "p9";
+				phy-mode =3D "10gbase-r";
+				sfp =3D <&sfp>;
+				managed =3D "in-band-status";
+			};
+
+			port@10 {
+				reg =3D <10>;
+				label =3D "cpu";
+				ethernet =3D <&cp0_eth0>;
+			};
+
+		};
+
+		mdio {
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+
+			switch0phy1: switch0phy1@1 {
+				reg =3D <0x1>;
+			};
+
+			switch0phy2: switch0phy2@2 {
+				reg =3D <0x2>;
+			};
+
+			switch0phy3: switch0phy3@3 {
+				reg =3D <0x3>;
+			};
+
+			switch0phy4: switch0phy4@4 {
+				reg =3D <0x4>;
+			};
+
+			switch0phy5: switch0phy5@5 {
+				reg =3D <0x5>;
+			};
+
+			switch0phy6: switch0phy6@6 {
+				reg =3D <0x6>;
+			};
+
+			switch0phy7: switch0phy7@7 {
+				reg =3D <0x7>;
+			};
+
+			switch0phy8: switch0phy8@8 {
+				reg =3D <0x8>;
+			};
+		};
+	};
 };
=20
 &cp0_xmdio {
--=20
2.33.0