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From:   Bhaskara Budiredla <bbudiredla@marvell.com>
To:     Bharat Bhushan <bbhushan2@marvell.com>,
        "will@kernel.org" <will@kernel.org>,
        "mark.rutland@arm.com" <mark.rutland@arm.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     Bharat Bhushan <bbhushan2@marvell.com>
Subject: RE: [PATCH v5 3/4] perf/marvell: cn10k DDR perfmon event overflow
 handling
Thread-Topic: [PATCH v5 3/4] perf/marvell: cn10k DDR perfmon event overflow
 handling
Thread-Index: AQHXw9eLecb4O5tsLUWUa4k2XOclQavYK/DA
Date:   Mon, 18 Oct 2021 04:37:49 +0000
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References: <20211018042015.25151-1-bbhushan2@marvell.com>
 <20211018042015.25151-4-bbhushan2@marvell.com>
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>Two fixed event counters starts counting from zero on overflow, so overflo=
w
>condition is when new count less than previous count. While eight
>programmable event counters freezes at maximum value. Also individual
>counter cannot be restarted, so need to restart all eight counters.
>
>Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
>---

Reviewed-by: Bhaskara Budiredla <bbudiredla@marvell.com>