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From:   Anup Patel <anup@brainfault.org>
Date:   Mon, 18 Oct 2021 11:01:28 +0530
Message-ID: <CAAhSdy3-hgdSH-B1cfO6C+5Fi-_DX8-ycRHi_ovVOzae1sRGzA@mail.gmail.com>
Subject: Re: [PATCH] riscv: fix misalgned trap vector base address
To:     Chen Lu <181250012@smail.nju.edu.cn>
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Alexandre Ghiti <alex@ghiti.fr>,
        Vitaly Wool <vitaly.wool@konsulko.com>,
        Sean Anderson <seanga2@gmail.com>,
        Kefeng Wang <wangkefeng.wang@huawei.com>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        Zihao Yu <yuzihao@ict.ac.cn>
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On Mon, Oct 18, 2021 at 10:52 AM Chen Lu <181250012@smail.nju.edu.cn> wrote:
>
> * The trap vector marked by label .Lsecondary_park should align on a
>   4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
>   and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
>

Please add "Fixes:" line here.

> Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>

Otherwise it looks good to me.

Reviewed-by: Anup Patel <anup.patel@wdc.com>

Regards,
Anup

> ---
>  arch/riscv/kernel/head.S | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
>         csrw CSR_SCRATCH, zero
>         ret
>
> +.align 2
>  .Lsecondary_park:
>         /* We lack SMP support or have too many harts, so park this hart */
>         wfi
> --
> 2.30.2
>
>
>