Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp2728302pxb; Mon, 18 Oct 2021 00:00:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx5nD5zHYgXU/9bJbaSpxA85F2jkgiRAdKiyNhbBzyBfpp78Rh3fvl6MFdd2GpBf1wUZBpS X-Received: by 2002:a05:6402:27cd:: with SMTP id c13mr41942791ede.351.1634540443488; Mon, 18 Oct 2021 00:00:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634540443; cv=none; d=google.com; s=arc-20160816; b=MWasgB4r/QDXsS1uGspHqFu6akmwmRxJyzF4HbaN+gYChdc6KUh/cVCRxGjzJZjLpe 1HxBo+zzqnKEpOTcLRibbuimDq7+JcxdFwZtEHslbckWxafgicxTUY6qYAwMDepJAQJf vKy1i17pnkC6Jce8GAe6Hygc+96rgFkdqm33uCZAshGrdoA3TcLuZKlCHuyCiKNy5+jq Nxey48k6wel9GjRFEQBS/AmQWkJS2gmmeU56Jero7JP3YQ/xr/fgVc5O7qspdhSa61AR b5wThGQnMZzjwtE+m4REaY/tVnq8iiAnTWIp/RG2HBaSppOWI0CL98KRJy5/WbpD2ByT cuZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-transfer-encoding :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=/dWA/sHgpP9RSW/1hSMxN+d6BC8SG2622y2VC8IxvYI=; b=DWSRHL8BrC4fL7i8tL3snnKnz302k/TwNaCAxIUnsKJKp6o4c6YZsUbqJP0SgigudA 8Xg//wZRc/3bMoHBwDkzZDFPIRmSunNNZqlEAqA8aXTsgZtv4A9tNpwfJNLUQufHygwn tS7RV8mh8bp/oc1HJVMo9EeqY77wHU5gyfjRbGnuahYjeOteXt10jhbUWYZXLEJwiu+x 7R4vFpWc/ofz7Egh5g6vQakdHvDuQGg0C51NVWef/Ol05xYsl/aURgVyZTXKQlqhuUYI 4Ymq6MjFbvUDYFBy1JS1kWno7TNYiJ36XThcxr+6zq50/rnmNnQqF7u8otYNORNuGscj 0JVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e22si21138905ejj.72.2021.10.17.23.59.59; Mon, 18 Oct 2021 00:00:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230265AbhJRG6P (ORCPT + 99 others); Mon, 18 Oct 2021 02:58:15 -0400 Received: from mga03.intel.com ([134.134.136.65]:25893 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229533AbhJRG6O (ORCPT ); Mon, 18 Oct 2021 02:58:14 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10140"; a="228131545" X-IronPort-AV: E=Sophos;i="5.85,381,1624345200"; d="scan'208";a="228131545" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2021 23:56:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,381,1624345200"; d="scan'208";a="489304579" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 17 Oct 2021 23:56:00 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 18 Oct 2021 09:55:59 +0300 Date: Mon, 18 Oct 2021 09:55:59 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Borislav Petkov Cc: Ser Olmy , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [regression] commit d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits") Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 15, 2021 at 01:04:28PM +0200, Borislav Petkov wrote: > Ok, here it is. Thanks. I got distracted by other shiny objects anyway, so wouldn't even have gotten to cooking up a proper patch until now. > > Ser, I'd appreciate you running it too, to make sure your box is still > ok. > > Thx. > > --- > From: Borislav Petkov > Date: Fri, 15 Oct 2021 12:46:25 +0200 > Subject: [PATCH] x86/fpu: Mask out the invalid MXCSR bits properly > MIME-Version: 1.0 > Content-Type: text/plain; charset=UTF-8 > Content-Transfer-Encoding: 8bit > > This is a fix for the fix (yeah, /facepalm). > > The correct mask to use is not the negation of the MXCSR_MASK but the > actual mask which contains the supported bits in the MXCSR register. > > Reported and debugged by Ville Syrj?l? > > Fixes: d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits") > Signed-off-by: Borislav Petkov > Cc: > Link: https://lore.kernel.org/r/YWgYIYXLriayyezv@intel.com > --- > arch/x86/kernel/fpu/signal.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c > index fa17a27390ab..831b25c5e705 100644 > --- a/arch/x86/kernel/fpu/signal.c > +++ b/arch/x86/kernel/fpu/signal.c > @@ -385,7 +385,7 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx, > return -EINVAL; > } else { > /* Mask invalid bits out for historical reasons (broken hardware). */ > - fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask; > + fpu->state.fxsave.mxcsr &= mxcsr_feature_mask; > } > > /* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */ > -- > 2.29.2 > > -- > Regards/Gruss, > Boris. > > https://people.kernel.org/tglx/notes-about-netiquette -- Ville Syrj?l? Intel