Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp2741266pxb; Mon, 18 Oct 2021 00:19:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGhRPf4WBIiblgpXEC6+Ss7XOpNV6KVLh3hRY0szCsDtnePo36kFgs+uUJe9z3W3b1bo8B X-Received: by 2002:a17:906:3bca:: with SMTP id v10mr27491494ejf.9.1634541594766; Mon, 18 Oct 2021 00:19:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634541594; cv=none; d=google.com; s=arc-20160816; b=XNefbPpepbzHYS0DLhoOoXrHNI+HPmp1SS4driOEdUOMR0VcwlsfPLJ0bubRpAwBuO Qz02VosGhhUVktDU8wQ71K0QBhzYibjRaesS0hzByLk/s1HFNXalRnel8OrrrG1qvnFn NQgsOI1C8A7r5fGSnOODUnv4sCLTX/XceESAaDS2o0DkeyRuvUk/zke1FG48PQnNWWeE uTjQxs7qoFJy/qf4ynsraQOkAD2jhnrbrWiLyGKOITxzR11g4hSKbhU+KeeR30o3ytt+ D3NIFVEqty3VGqFL2UFHDAYqWoWyNoniLiPnz1tNDrUU2Q/FT2wUt0YOW+p7s3FuwP6t J3PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from :dkim-signature; bh=tBE9gpFLaTdVJ/JmeejJpC/B5K1DEYpgVD8Zzk/KwLA=; b=HQDyFgOIYw+OQrsFRU3lUGsiHegEPc3CwzzMBpxkQcxyxyk2MLnGoy6wDE+yLcV/W3 MhX6oQcGlMiDLoNSSvkXrWwiy7/8HhexvXABbmfZBroETgFQQ91mKdZ8/mzuNdTvLeDK w1y3wMVE1DMmnYR8+O+gZxId6sBh9vc0a9dQQrU+OASdma1urT6oED5SZLIp+9yQIjFO 08+fFAGE3WFsEF6EhDeHwqiX23BI+k7kFbPrdeOycFcWm3CULAf55aZGDXpt5klaolpn IonLWkhyrK/wJF6eTOaCSlguRIqgaKNZIWkqp5cO+/UJ9e1IhgygZFt8VqB/RE5Sowt3 Zv/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=DlBW55Cx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w15si18168821eds.603.2021.10.18.00.19.30; Mon, 18 Oct 2021 00:19:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=DlBW55Cx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230326AbhJRHTx (ORCPT + 99 others); Mon, 18 Oct 2021 03:19:53 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:2389 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230114AbhJRHTw (ORCPT ); Mon, 18 Oct 2021 03:19:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1634541462; x=1666077462; h=from:to:cc:subject:date:message-id:mime-version; bh=tBE9gpFLaTdVJ/JmeejJpC/B5K1DEYpgVD8Zzk/KwLA=; b=DlBW55Cx91nqKZt5CKVRdt6GCnaC1WGNu1j0u1MFvYVzHzW7T6ubTM8c IL/3Rl0jaYM2Bu9mfbN5In+WBfibvqJhQa7IknpNFjUtl6vqsUZJBcSiG 8fkLRb+oVLTNVcwAAxynEK6dMkdKh3WK0CHSe3oIVwGs8joo/nTx/t9Z/ c=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 18 Oct 2021 00:17:42 -0700 X-QCInternal: smtphost Received: from nalasex01a.na.qualcomm.com ([10.47.209.196]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2021 00:17:40 -0700 Received: from jprakash-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Mon, 18 Oct 2021 00:17:35 -0700 From: Jishnu Prakash To: , , , , , , , , , CC: , , , , "Jishnu Prakash" Subject: [PATCH 0/2] thermal: qcom: Add support for PMIC5 Gen2 ADC_TM Date: Mon, 18 Oct 2021 12:47:07 +0530 Message-ID: <1634541429-3215-1-git-send-email-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PMIC5 Gen2 ADC_TM is supported on PMIC7 chips and is a close counterpart of PMIC7 ADC. It has the same functionality as PMIC5 ADC_TM, to support generating interrupts on ADC value crossing upper or lower thresholds for monitored channels. Jishnu Prakash (2): dt-bindings: thermal: qcom: add PMIC5 Gen2 ADC_TM bindings thermal: qcom: add support for PMIC5 Gen2 ADCTM .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 83 +++- drivers/iio/adc/qcom-vadc-common.c | 187 +++++++++ drivers/thermal/qcom/qcom-spmi-adc-tm5.c | 431 ++++++++++++++++++++- include/linux/iio/adc/qcom-vadc-common.h | 2 + 4 files changed, 692 insertions(+), 11 deletions(-) -- 2.7.4