Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp3062709pxb; Mon, 18 Oct 2021 07:31:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyF77PnJ5JR7EPnfXWnfHZIjoXpZn2RwZAj1IpcNmK2dp5HgS5FrH2Iu+98nyRt5CRnCWHP X-Received: by 2002:a5d:6943:: with SMTP id r3mr27970722wrw.267.1634567513341; Mon, 18 Oct 2021 07:31:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634567513; cv=none; d=google.com; s=arc-20160816; b=yePJy0yorC6JVLLYDocUK/YY2dYiBh/cNux20hOX/+MHRFf5WrYeq/FhExzTspht15 ldANek3JURgaEexNEpF1/G9ymbGXhuHYPORxd7+jRa4edH7K4aaHigQYoW4mPV1f8wbI pnTntjekbcMgvQe95+d/4cOnn9T38dKwHpFeclMmNi2fmKeGAzlv+WgXisFu5hO1I49Q VsDeSJDY1+mqyxlSJ68UgE7Y0cU1hZeVjMEoIUcMD4vhvzOJZm0Nno0hgpFk0QUPeQ6u /aTT7diBb+F0vBmUzomtu6g223aXj6ylY70b/1bwVfhFBAp1FbXInV+WU+QRokWwSlcR OzfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PlRyqVZs8t2GxRCJeGwHfM08zQltefexaW1+bSnykxM=; b=dTV3bIdOUdIuHukOuNI1A1c2HLpBK1Zx6lRdfD89jdH2M1bGP6GySH5vFDfK3B+y3y ZMHlW0jMoadY5HfvSvkg94M38/tkCsoIJgdna4w5cx4HB0+bXPxt+qrQTqgKKiLrwckO hhjOjR8WxZQ1adsdw7E+VOQNTNSMD5B2tgcEEZRuEf/D7welKt/jnzUDM1Dw5jcoc48C J05j/WKpjGv9DjahpwZNGDH66WMvFTnlmjNIEYmil6JisCLy82GOZdrGaztPAF/qynp0 o3Qqvxnd3vxFhbVRSwRzXZNpjtiqti02IiIHNP5m4WvozPs7JlXxKdsq9CCM83vbvCio 52mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=lVKEYO5E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s13si20831725eju.701.2021.10.18.07.31.29; Mon, 18 Oct 2021 07:31:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=lVKEYO5E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232012AbhJRObC (ORCPT + 99 others); Mon, 18 Oct 2021 10:31:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231997AbhJROa7 (ORCPT ); Mon, 18 Oct 2021 10:30:59 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80609C061745 for ; Mon, 18 Oct 2021 07:28:48 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id o24-20020a05600c511800b0030d9da600aeso140460wms.4 for ; Mon, 18 Oct 2021 07:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PlRyqVZs8t2GxRCJeGwHfM08zQltefexaW1+bSnykxM=; b=lVKEYO5EP1/doQX6tasKJjzKVsdtxdzU6s9kAJW8P7SiRFhfArSu/0ywEfNA/NMh28 wsRMXPYF5Ktxw1PGgnzOi5OPWfe0CsVlvWZ0B6uyjScv/92Lk47pDqX+jheiD9yMT+H3 gAxH5/nHZCZMYAd0v7mW2m+dlz5SNUVDIniihpgpLK/RH46FcORnt4JNRux4iBk/CsxU SlF7HJDRH1v8ttdVx/WQvxDZvWw9uh7pgfDmZBKpSiyzvlzbVy4+xOse9kUosIFMOzZZ cow+3riXUiHEJV5uHisbdbK6iys1h0EDCaT9505eA/5tpsxmCDw6v9l5gEUUP3IiapZD zaeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PlRyqVZs8t2GxRCJeGwHfM08zQltefexaW1+bSnykxM=; b=1Sg8h8nXBROnS3qIMKutlOWeLClmW4ddxW/pbewgdpcOy+8ke2Niji7sAP2Y3vEV9O nds35J/wfbXhK82kEVjSe2z0neany8dlo6giszMw6w7VrPSUMGyWhpt5tVs+5BbfwHn3 jRtrnvcb4xS6MnDdUIEPayXkqMJQWu9jZaHnUlAT+TOWDMy12VGJ2wphwk49GZEzivth 7cDyJHY0TUBAjHK8OibP1z00qLDzw/Uiy0jf6VEV9EqexsXF06cVOZWxpDRkCWn8MDol 1PI9tW89iQMHSNLBrJ65quK70X+yDlqRiiqXNPfJG3YEVGa2Y4eYnUG13IWzRw/73/S5 dPiQ== X-Gm-Message-State: AOAM531/k5GGrArUnR5o+DIRP0Vt8wXnh8rRX5WYebB3hOSJk5ZHEHDK SXmNZP3z4JDHMgXQbNfCToHT2A== X-Received: by 2002:a05:600c:a4b:: with SMTP id c11mr30050047wmq.97.1634567326960; Mon, 18 Oct 2021 07:28:46 -0700 (PDT) Received: from localhost.localdomain ([2001:861:44c0:66c0:2dd7:d5eb:6e87:f924]) by smtp.gmail.com with ESMTPSA id b3sm12908495wrp.52.2021.10.18.07.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 07:28:46 -0700 (PDT) From: Neil Armstrong To: tomba@kernel.org Cc: linux-omap@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, Benoit Parrot , Neil Armstrong Subject: [PATCH v6 2/9] drm/omap: Add ability to check if requested plane modes can be supported Date: Mon, 18 Oct 2021 16:28:35 +0200 Message-Id: <20211018142842.2511200-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211018142842.2511200-1-narmstrong@baylibre.com> References: <20211018142842.2511200-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5884; i=narmstrong@baylibre.com; h=from:subject; bh=m1fui6vsNAviHm9JjbpK2UEIata+oUxTAJinjmkQeMU=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBhbYSF6EJImsbCEwAk3lfi3qnwenhpmDpa0nj1zxGv yId8A/eJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYW2EhQAKCRB33NvayMhJ0a2dD/ sGpM257UvyBFfJjFPYFW1b6eUqciEKtf4xSrPMroDyewaiQz0lKe7fdf4PXy8ndsI769SXeDg1J7JO BibYt88P5ZTXbYc5DLr5n6hsitgS/o+CzwXyAAmWPtjwiJJg/VcjYQvWmi3dLtoX1kW8T8ecf2Wh3T Dao63dP4zciFu9DSstOcPOcB5lDNw7Wp7t52RbSAzsfG3QO3DQjSXWGnaU3mGz08wItB0n9W2Ydfva aVsm2y21vKewMDLOUoEAMMf6BBCnCDq2lRGYiifA112EcfxAcuOPC+gTXnQgNj2jgzvrIgtP9D28to ukFAAAQXHNw0/hUiSmU8mVeDX4PVxZN/JiO+SyChpEoACzwJMxbzUS1FQHSCORKO3ptitD6TGD37sH Ya5HIP09T8PX1z6KfqAEuZ1rVfhAdOZDhRueW7epuenbBEP1ldxWUEpGJ0IRL5NcwgJjohgugsNSdH Rna19F+Vzv1Jy2y4zrdC6aK0sRt7TSW95iHUFZMFLfKz8a34RAfRv3wajguwFZiZmbEKRJoL0H1wnj 885Gdnd0cIDw/EtDER0X7S4RczpsZv9L76BLWT1m5flXYdgmunWbfvHW+ygFkvdBUAwqiATsnGKPwu VPmuFvmakOfItJs5cblxAkrVB9cp3pri4g7/vmycpAy1rYR2IG7ffIBG0e0g== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benoit Parrot We currently assume that an overlay has the same maximum width and maximum height as the overlay manager. This assumption is incorrect. On some variants the overlay manager maximum width is twice the maximum width that the overlay can handle. We need to add the appropriate data per variant as well as export a helper function to retrieve the data so check can be made dynamically in omap_plane_atomic_check(). Signed-off-by: Benoit Parrot Signed-off-by: Neil Armstrong --- drivers/gpu/drm/omapdrm/dss/dispc.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/omapdrm/dss/dss.h | 2 ++ drivers/gpu/drm/omapdrm/omap_plane.c | 14 ++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 5619420cc2cc..5ac90ba6b76d 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -92,6 +92,8 @@ struct dispc_features { u8 mgr_height_start; u16 mgr_width_max; u16 mgr_height_max; + u16 ovl_width_max; + u16 ovl_height_max; unsigned long max_lcd_pclk; unsigned long max_tv_pclk; unsigned int max_downscale; @@ -2599,6 +2601,12 @@ static int dispc_ovl_calc_scaling(struct dispc_device *dispc, return 0; } +void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height) +{ + *width = dispc->feat->ovl_width_max; + *height = dispc->feat->ovl_height_max; +} + static int dispc_ovl_setup_common(struct dispc_device *dispc, enum omap_plane_id plane, enum omap_overlay_caps caps, @@ -4240,6 +4248,8 @@ static const struct dispc_features omap24xx_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 66500000, .max_downscale = 2, /* @@ -4278,6 +4288,8 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, .max_downscale = 4, @@ -4313,6 +4325,8 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, .max_downscale = 4, @@ -4348,6 +4362,8 @@ static const struct dispc_features omap36xx_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, .max_downscale = 4, @@ -4383,6 +4399,8 @@ static const struct dispc_features am43xx_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, .max_downscale = 4, @@ -4418,6 +4436,8 @@ static const struct dispc_features omap44xx_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 170000000, .max_tv_pclk = 185625000, .max_downscale = 4, @@ -4457,6 +4477,8 @@ static const struct dispc_features omap54xx_dispc_feats = { .mgr_height_start = 27, .mgr_width_max = 4096, .mgr_height_max = 4096, + .ovl_width_max = 2048, + .ovl_height_max = 4096, .max_lcd_pclk = 170000000, .max_tv_pclk = 186000000, .max_downscale = 4, diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index a547527bb2f3..14c39f7c3988 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -397,6 +397,8 @@ int dispc_get_num_mgrs(struct dispc_device *dispc); const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, enum omap_plane_id plane); +void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height); + u32 dispc_read_irqstatus(struct dispc_device *dispc); void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask); void dispc_write_irqenable(struct dispc_device *dispc, u32 mask); diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index c3de4f339387..846698c21a4a 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -111,12 +111,19 @@ static int omap_plane_atomic_check(struct drm_plane *plane, { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); + struct omap_drm_private *priv = plane->dev->dev_private; struct drm_crtc_state *crtc_state; + u32 max_width, max_height; + u16 width, height; int ret; if (!new_plane_state->fb) return 0; + dispc_ovl_get_max_size(priv->dispc, &width, &height); + max_width = width << 16; + max_height = height << 16; + /* crtc should only be NULL when disabling (i.e., !new_plane_state->fb) */ if (WARN_ON(!new_plane_state->crtc)) return 0; @@ -151,6 +158,13 @@ static int omap_plane_atomic_check(struct drm_plane *plane, if (new_plane_state->crtc_y + new_plane_state->crtc_h > crtc_state->adjusted_mode.vdisplay) return -EINVAL; + /* Make sure dimensions are within bounds. */ + if (new_plane_state->src_h > max_height || new_plane_state->crtc_h > height) + return -EINVAL; + + if (new_plane_state->src_w > max_width || new_plane_state->crtc_w > width) + return -EINVAL; + if (new_plane_state->rotation != DRM_MODE_ROTATE_0 && !omap_framebuffer_supports_rotation(new_plane_state->fb)) return -EINVAL; -- 2.25.1