Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp277880pxb; Tue, 19 Oct 2021 02:41:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNR53zRu7hHTJL24w6q0GKnQq/pggx0bEa7CZix/EtRE0T1wEN1cCSoUUe9Vu3/l3/3i5X X-Received: by 2002:a17:907:6e12:: with SMTP id sd18mr12967389ejc.157.1634636484632; Tue, 19 Oct 2021 02:41:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634636484; cv=none; d=google.com; s=arc-20160816; b=R2RSAegiMFxmMkBvToBJLhxZp0xGvnDcBZ/z2YTnPsbEOvP4g4Hb9GJWFioIiLKcBA 8dxsePIRxwx5yj68vEAuSxSQ+WlN679ElL0MnEAGnPwJXXfAFOTURUikcIbn1ANhMFme Xl2wHNA0OO5KvlvsipgiiaTvFN7BdY4mrsVX0hzm2Gh6N88kktWaqxb/qFDKl2+9JWpG 3Ax/uHVxIUWiEJEasTNoQCmZSV4jndBk/LzMdjcZ8I6+UehlZVcbB8n1vDxqrWbf3NFz /nuHwzoBZ2+HDNNeqYQOrfeAkvzrUqH2Iqh/wnwzVocDEODvI8j8scHrI7meadNLM2nX 1cKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=ND/+F3Ar6OquSntMCxz9qgsi04nnrmfHfmUAomzm/4I=; b=bmMcrwiv5+GbMrYmzZU0L9Mej/VEg706p9KQ3qxoD//V0htJFkWcB/z5Z8r9bLbAiG VCGW//YAMkU2O7TmxWvs/n/+RMMtS5EujuoSrtPHv5P26EkJZnSs+pBbGR+8rq5W0Y8g L91UaSowNTOIXh8z/Sbz1ZnW6Zhpvgrq/s8qksNVZg2X6T37pWhbFafuXEkoaKw51mHH 2kZADtIHtyuvpNVhCNobhZcLvqAcPnEytPKlg0815G8qPhcodF+MtsOVMehP3HA4sUVi J2pQ3SorKQvfwfhihQNB8cNGAAtSsUe13EB+Eg87T3HULTZZTvWMkJ06hU0smtNebCu8 pIPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FPakQL+O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v4si20820448edi.519.2021.10.19.02.41.00; Tue, 19 Oct 2021 02:41:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FPakQL+O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235034AbhJSJjb (ORCPT + 99 others); Tue, 19 Oct 2021 05:39:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234914AbhJSJja (ORCPT ); Tue, 19 Oct 2021 05:39:30 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1E2BC061745 for ; Tue, 19 Oct 2021 02:37:17 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id qe4-20020a17090b4f8400b0019f663cfcd1so1563679pjb.1 for ; Tue, 19 Oct 2021 02:37:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ND/+F3Ar6OquSntMCxz9qgsi04nnrmfHfmUAomzm/4I=; b=FPakQL+OMRNJjPfkzZN3ZBE8vdbu/9WnnBjj5mkIEUhTkx7Rqb3FRIWk2gTwmabN7M HxNn2wpfA4/+8yXJ8q6aEc5XptfDatWuu5senZReW2tIxnCl+HFfZfi9PSRNGuEbADeY ZEYbYrsxuWJ68e0fiDjYy9jUS6UtwJuk2HeCVJoqCWTKfim7fNlioHJVMpSIa2OuEnNk YggCW/wWGMuA34KEplUEC0mqlRVGginPMszr7va+pAIXfa+mioE7T38vVgbWQ/ScPKu3 /yu8jhTUMmg6M4x1xPeZgyGRMSR7Vs8+LYL45JPI7o3IFKVTfcM+8aFZ0ER4GSZGA6Ri Y4eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ND/+F3Ar6OquSntMCxz9qgsi04nnrmfHfmUAomzm/4I=; b=ugMEcoyOgjwCm+sSwCn9P9MWrh2lkCNIe1rxEq0SUaRkDvFO98rqtRWJNlM3husIim wFmyS/l18AxuVnQaE+pegXrp/bReccSVm6DcHQ5XpK1nmKRPgUUiPIXfbvMFFh6FKN6X fkWsig6+JdtTRxkAAwtS/ENlKBJsLQKUQ5Yc/fq0BG4kgBPZ/ORi8SQAYtQl8OJiBXek N8LhnuvcqSpXS8vq+WI55Fk8xth05g5gFW6Jf71OgYsrpBbMt2Q9RwCCmjf3VP2t+eQY ZBbg+Jfue5kV46PBjqlg+KL3b6RClumNB6lYYs4baO6DY5b4GndyAryw9d5YVxmtAavS lWtw== X-Gm-Message-State: AOAM532u5AYCNrksv1A5xAFHkbSZnb9GzjItP93W2sz9Mv9rc6O1I2O9 hU8w4cn2iIhV87qmsyr7YxSOVDCFBRKFjMN61o2tpw== X-Received: by 2002:a17:90b:4c0d:: with SMTP id na13mr5260275pjb.232.1634636237402; Tue, 19 Oct 2021 02:37:17 -0700 (PDT) MIME-Version: 1.0 References: <20211002233447.1105-1-digetx@gmail.com> <20211002233447.1105-5-digetx@gmail.com> In-Reply-To: <20211002233447.1105-5-digetx@gmail.com> From: Robert Foss Date: Tue, 19 Oct 2021 11:37:06 +0200 Message-ID: Subject: Re: [PATCH v1 4/5] drm/bridge: tc358768: Disable non-continuous clock mode To: Dmitry Osipenko Cc: Thierry Reding , Andrzej Hajda , Neil Armstrong , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maxim Schwalm , Andreas Westman Dorcsak , Peter Ujfalusi , David Airlie , Daniel Vetter , dri-devel , linux-tegra@vger.kernel.org, linux-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 3 Oct 2021 at 01:35, Dmitry Osipenko wrote: > > Non-continuous clock mode doesn't work because driver doesn't support it > properly. The bridge driver programs wrong bitfields that are required by > the non-continuous mode (BTACNTRL1 register bitfields are swapped in the > code), but fixing them doesn't help. > > Display panel of ASUS Transformer TF700T tablet supports non-continuous > mode and display doesn't work at all using that mode. There are no > device-trees that are actively using this DSI bridge in upstream yet, > so clearly the broken mode wasn't ever tested properly. It's a bit too > difficult to get LP mode working, hence let's disable the offending mode > for now and fall back to continuous mode. > > Tested-by: Andreas Westman Dorcsak # Asus TF700T > Tested-by: Maxim Schwalm #TF700T > Signed-off-by: Dmitry Osipenko > --- > drivers/gpu/drm/bridge/tc358768.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c > index 5b3f8723bd3d..cfceba5ef3b8 100644 > --- a/drivers/gpu/drm/bridge/tc358768.c > +++ b/drivers/gpu/drm/bridge/tc358768.c > @@ -631,6 +631,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) > { > struct tc358768_priv *priv = bridge_to_tc358768(bridge); > struct mipi_dsi_device *dsi_dev = priv->output.dev; > + unsigned long mode_flags = dsi_dev->mode_flags; > u32 val, val2, lptxcnt, hact, data_type; > const struct drm_display_mode *mode; > u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk; > @@ -638,6 +639,11 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) > const u32 internal_delay = 40; > int ret, i; > > + if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { > + dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n"); > + mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; > + } > + > tc358768_hw_enable(priv); > > ret = tc358768_sw_reset(priv); > @@ -776,7 +782,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) > val |= BIT(i + 1); > tc358768_write(priv, TC358768_HSTXVREGEN, val); > > - if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) > + if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) > tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); > > /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ > @@ -864,7 +870,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) > if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) > val |= TC358768_DSI_CONTROL_TXMD; > > - if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) > + if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) > val |= TC358768_DSI_CONTROL_HSCKMD; > > if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) > -- Reviewed-by: Robert Foss