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[23.128.96.18]) by mx.google.com with ESMTP id lw6si2556449pjb.95.2021.10.19.11.18.07; Tue, 19 Oct 2021 11:18:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234665AbhJSSRX (ORCPT + 99 others); Tue, 19 Oct 2021 14:17:23 -0400 Received: from mga11.intel.com ([192.55.52.93]:50074 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232130AbhJSSRX (ORCPT ); Tue, 19 Oct 2021 14:17:23 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10142"; a="226054219" X-IronPort-AV: E=Sophos;i="5.87,164,1631602800"; d="scan'208";a="226054219" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2021 11:15:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,164,1631602800"; d="scan'208";a="494226142" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga008.jf.intel.com with SMTP; 19 Oct 2021 11:15:03 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 19 Oct 2021 21:15:02 +0300 Date: Tue, 19 Oct 2021 21:15:02 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Lyude Paul Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Sean Paul , open list Subject: Re: [PATCH v3 5/5] drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs() Message-ID: References: <20211006024018.320394-1-lyude@redhat.com> <20211006024018.320394-6-lyude@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211006024018.320394-6-lyude@redhat.com> X-Patchwork-Hint: comment Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 05, 2021 at 10:40:18PM -0400, Lyude Paul wrote: > Hooray! We've managed to hit enough bugs upstream that I've been able to > come up with a pretty solid explanation for how backlight controls are > actually supposed to be detected and used these days. As well, having the > rest of the PWM bits in VESA's backlight interface implemented seems to > have fixed all of the problematic brightness controls laptop panels that > we've hit so far. > > So, let's actually document this instead of just calling the laptop panels > liars. As well, I would like to formally apologize to all of the laptop > panels I called liars. I'm sorry laptop panels, hopefully you can all > forgive me and we can move past this~ > > Signed-off-by: Lyude Paul > --- > .../drm/i915/display/intel_dp_aux_backlight.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > index 91daf9ab50e8..04a52d6a74ed 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > @@ -455,11 +455,17 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector) > } > > /* > - * A lot of eDP panels in the wild will report supporting both the > - * Intel proprietary backlight control interface, and the VESA > - * backlight control interface. Many of these panels are liars though, > - * and will only work with the Intel interface. So, always probe for > - * that first. > + * Since Intel has their own backlight control interface, the majority of machines out there > + * using DPCD backlight controls with Intel GPUs will be using this interface as opposed to > + * the VESA interface. However, other GPUs (such as Nvidia's) will always use the VESA > + * interface. This means that there's quite a number of panels out there that will advertise > + * support for both interfaces, primarily systems with Intel/Nvidia hybrid GPU setups. > + * > + * There's a catch to this though: on many panels that advertise support for both > + * interfaces, the VESA backlight interface will stop working once we've programmed the > + * panel with Intel's OUI - which is also required for us to be able to detect Intel's > + * backlight interface at all. This means that the only sensible way for us to detect both > + * interfaces is to probe for Intel's first, and VESA's second. > */ You know a lot more about this than I do. Acked-by: Ville Syrj?l? > if (try_intel_interface && intel_dp_aux_supports_hdr_backlight(connector)) { > drm_dbg_kms(dev, "Using Intel proprietary eDP backlight controls\n"); > -- > 2.31.1 -- Ville Syrj?l? Intel