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[23.128.96.18]) by mx.google.com with ESMTP id n26si2765805eda.167.2021.10.20.06.37.05; Wed, 20 Oct 2021 06:37:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230061AbhJTNgW (ORCPT + 99 others); Wed, 20 Oct 2021 09:36:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:43280 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229639AbhJTNgW (ORCPT ); Wed, 20 Oct 2021 09:36:22 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 99234611C6; Wed, 20 Oct 2021 13:34:07 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mdBjJ-000RVA-Hw; Wed, 20 Oct 2021 14:34:05 +0100 Date: Wed, 20 Oct 2021 14:34:05 +0100 Message-ID: <875ytrddma.wl-maz@kernel.org> From: Marc Zyngier To: Guo Ren Cc: Samuel Holland , Anup Patel , Atish Patra , Thomas Gleixner , Palmer Dabbelt , Heiko =?UTF-8?B?U3TDvGJuZXI=?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support In-Reply-To: References: <20211016032200.2869998-1-guoren@kernel.org> <20211016032200.2869998-2-guoren@kernel.org> <8be1bdbd-365d-cd28-79d7-b924908f9e39@sholland.org> <8735oxuxlq.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: guoren@kernel.org, samuel@sholland.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 19 Oct 2021 14:27:02 +0100, Guo Ren wrote: > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier wrote: > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > Guo Ren wrote: > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > in a separate bit, then you need to track this by yourself in the > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > the CLAIM register in this case, though I have no idea whether this > > > > breaks > > > > the HW interrupt state or not. > > > The problem is when enable bit is 0 for that irq_number, > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > the hw state machine. Then this irq would enter in ack state and no > > > continues irqs could come in. > > > > Really? This means that you cannot mask an interrupt while it is being > > handled? How great... > If the completion ID does not match an interrupt source that is > currently enabled for the target, the completion is silently ignored. > So, C9xx completion depends on enable-bit. Is that what the PLIC spec says? Or what your implementation does? I can understand that one implementation would be broken, but if the PLIC architecture itself is broken, that's far more concerning. M. -- Without deviation from the norm, progress is not possible.