Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp232193pxb; Wed, 20 Oct 2021 21:01:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9bg1JY8vFB2T/5MFpQl5E+3SD+TElb0SJLNc4KlnOWwljJIe6TVfEbxmwyNku4pkjuEDQ X-Received: by 2002:a17:90a:9404:: with SMTP id r4mr3571100pjo.240.1634788859791; Wed, 20 Oct 2021 21:00:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634788859; cv=none; d=google.com; s=arc-20160816; b=E2Sodv2bqZYjvXFK1PJHZMgyjBiSgOi7E3uT4LsDTE5N7eo3TAzVajtRiFkTmX0JpL xWHADtwEIVibcmqtJ5+M8YB/3Cq418wxLyx+gVXntq+4Fu/1q/BT/ZW16966bWinvc3m UJq4sxSaT225lfR7Lg9WkqjMG16+ZNVOxQNMAqartDJ4vHossPFY78yj/zMukGUQGpuI QBG+6iOEm7C7hv2gJDFeOVni3iOMA3Yfo3CvwVmUKAEqc1pcI9CoXOLeaSfBbiu6pzHl TemHe3vsAntHkkz5YBC5DCPmP9fCXJocfciKHLn3kjQ6m0I0/MYk7Mqwc+BhpY8xwOZx XbLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=wPwx+TVC1PQtlKRpxg/TO6qhU47I8gevt12Wm0PZLU0=; b=LPwJj8SJpI6T6rJuJFfUsggqKkY28w+mACknUJRsGdAGQeYz9fW/uHVmlIPR35pUyR vMTIBgpsMF/wE2JBG35kghLtpripmiUywcsoIViI5EIoGnPsDGVGp9nu4j4oiQOhhkN+ elEyC4veJtjlqRWeZ8nzXhbpq0tACV14CnRe2Skl3ReY61c0X4jRXFX4TJqRLFzPSuVc Iy9nMq3IH2Jzhbj0v9zzvaofQicvJzk+mK8p2BNnK22JRhZad/SM0kcXjfrvNT/w0dCD JL9XwrnZOZMJT7yizRmzEOsjimhgCN653+hAWRKV6w/7jmdFywJIwaHDi8Bh5H2XYW/r 7I4w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id nu15si11400334pjb.179.2021.10.20.21.00.21; Wed, 20 Oct 2021 21:00:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229567AbhJUEBK (ORCPT + 99 others); Thu, 21 Oct 2021 00:01:10 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:36024 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229450AbhJUEBJ (ORCPT ); Thu, 21 Oct 2021 00:01:09 -0400 X-UUID: bac1888e3b3d40c59257dc7eb9aad423-20211021 X-UUID: bac1888e3b3d40c59257dc7eb9aad423-20211021 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1747227135; Thu, 21 Oct 2021 11:58:46 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Oct 2021 11:58:45 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Oct 2021 11:58:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 21 Oct 2021 11:58:45 +0800 From: YC Hung To: , , , CC: , , , , , , , , Subject: [PATCH v2 0/2] Add code to manage DSP clocks and provide dts-binding document Date: Thu, 21 Oct 2021 11:58:39 +0800 Message-ID: <20211021035841.2365-1-yc.hung@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "yc.hung" This code is based on top of SOF topic/sof-dev branch and we want to have a review with ALSA and device Tree communities the it will be merged to SOF tree and then merged into ALSA tree. It provides two patches, one is for mt8195 dsp clocks related. Another is for mt8195 dsp dts binding decription. YC Hung (2): ASoC: SOF: mediatek: Add mt8195 dsp clock support dt-bindings: dsp: mediatek: Add mt8195 DSP binding support .../bindings/dsp/mtk,mt8195-dsp.yaml | 139 +++++++++++++++ sound/soc/sof/mediatek/mt8195/Makefile | 2 +- sound/soc/sof/mediatek/mt8195/mt8195-clk.c | 164 ++++++++++++++++++ sound/soc/sof/mediatek/mt8195/mt8195-clk.h | 29 ++++ sound/soc/sof/mediatek/mt8195/mt8195.c | 23 ++- 5 files changed, 354 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/dsp/mtk,mt8195-dsp.yaml create mode 100644 sound/soc/sof/mediatek/mt8195/mt8195-clk.c create mode 100644 sound/soc/sof/mediatek/mt8195/mt8195-clk.h -- 2.18.0