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From:   Bough Chen <haibo.chen@nxp.com>
To:     Chester Lin <clin@suse.com>, Ulf Hansson <ulf.hansson@linaro.org>,
        dl-S32 <S32@nxp.com>, dl-linux-imx <linux-imx@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>
CC:     Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Radu-nicolae Pirea (OSS)" <radu-nicolae.pirea@oss.nxp.com>,
        =?utf-8?B?QW5kcmVhcyBGw6RyYmVy?= <afaerber@suse.de>,
        Matthias Brugger <mbrugger@suse.com>,
        "Ivan T . Ivanov" <iivanov@suse.de>, "Lee, Chun-Yi" <jlee@suse.com>
Subject: RE: [RFC PATCH 2/3] mmc: sdhci-esdhc-imx: add NXP S32G2 support
Thread-Topic: [RFC PATCH 2/3] mmc: sdhci-esdhc-imx: add NXP S32G2 support
Thread-Index: AQHXxks6gGPmv4zpGkyIzNunP0BeP6vdC0Hg
Date:   Thu, 21 Oct 2021 07:21:39 +0000
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References: <20211021071333.32485-1-clin@suse.com>
 <20211021071333.32485-3-clin@suse.com>
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> -----Original Message-----
> From: Chester Lin [mailto:clin@suse.com]
> Sent: 2021=E5=B9=B410=E6=9C=8821=E6=97=A5 15:14
> To: Ulf Hansson <ulf.hansson@linaro.org>; dl-S32 <S32@nxp.com>; =
dl-linux-imx
> <linux-imx@nxp.com>; Bough Chen <haibo.chen@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; linux-mmc@vger.kernel.org
> Cc: Rob Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>;
> Sascha Hauer <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; Radu-nicolae Pirea (OSS)
> <radu-nicolae.pirea@oss.nxp.com>; Andreas F=C3=A4rber =
<afaerber@suse.de>;
> Matthias Brugger <mbrugger@suse.com>; Ivan T . Ivanov =
<iivanov@suse.de>;
> Lee, Chun-Yi <jlee@suse.com>; Chester Lin <clin@suse.com>
> Subject: [RFC PATCH 2/3] mmc: sdhci-esdhc-imx: add NXP S32G2 support
>=20
> Support the SDHCI controller found on NXP S32G2 platform. The new flag
> ESDHC_FLAG_SKIP_ERR004536 is used because the hardware erratum bit is
> not applicable for S32G2.

What's this bit7 definition on S32G2 usdhc?  Any issue if clear bit 7?

Best Regards
Haibo Chen
>=20
> Signed-off-by: Chester Lin <clin@suse.com>
> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index f18d169bc8ff..d0f7d46a0354 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -196,6 +196,9 @@
>   */
>  #define ESDHC_FLAG_BROKEN_AUTO_CMD23	BIT(16)
>=20
> +/* ERR004536 is not applicable for the IP  */
> +#define ESDHC_FLAG_SKIP_ERR004536	BIT(17)
> +
>  enum wp_types {
>  	ESDHC_WP_NONE,		/* no WP, neither controller nor gpio */
>  	ESDHC_WP_CONTROLLER,	/* mmc controller internal WP */
> @@ -289,6 +292,13 @@ static const struct esdhc_soc_data
> usdhc_imx7d_data =3D {
>  			| ESDHC_FLAG_BROKEN_AUTO_CMD23,
>  };
>=20
> +static struct esdhc_soc_data usdhc_s32g2_data =3D {
> +	.flags =3D ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
> +			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> +			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
> +			| ESDHC_FLAG_SKIP_ERR004536,
> +};
> +
>  static struct esdhc_soc_data usdhc_imx7ulp_data =3D {
>  	.flags =3D ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
>  			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 @@ -347,6
> +357,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] =3D {
>  	{ .compatible =3D "fsl,imx7ulp-usdhc", .data =3D =
&usdhc_imx7ulp_data, },
>  	{ .compatible =3D "fsl,imx8qxp-usdhc", .data =3D =
&usdhc_imx8qxp_data, },
>  	{ .compatible =3D "fsl,imx8mm-usdhc", .data =3D &usdhc_imx8mm_data, =
},
> +	{ .compatible =3D "nxp,s32g2-usdhc", .data =3D &usdhc_s32g2_data, },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); @@ -1359,8 +1370,10 @@
> static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
>  		 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
>  		 * TO1.1, it's harmless for MX6SL
>  		 */
> -		writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
> -			host->ioaddr + 0x6c);
> +		if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
> +			writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
> +				host->ioaddr + 0x6c);
> +		}
>=20
>  		/* disable DLL_CTRL delay line settings */
>  		writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
> --
> 2.30.0


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