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Date:   Thu, 21 Oct 2021 22:38:07 +0800
From:   Chester Lin <clin@suse.com>
To:     "Radu Nicolae Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
CC:     s32@nxp.com, Andreas =?iso-8859-1?Q?F=E4rber?= <afaerber@suse.de>,
        Matthias Brugger <mbrugger@suse.com>,
        devicetree@vger.kernel.org, Ulf Hansson <ulf.hansson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, Dong Aisheng <aisheng.dong@nxp.com>,
        BOUGH CHEN <haibo.chen@nxp.com>,
        "Ivan T . Ivanov" <iivanov@suse.de>, "Lee, Chun-Yi" <jlee@suse.com>
Subject: Re: [PATCH 3/3] arm64: dts: s32g2: add USDHC support
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Hi Radu,

On Thu, Oct 21, 2021 at 04:32:52PM +0300, Radu Nicolae Pirea (NXP OSS) wrot=
e:
> Hi Chester,
>=20
> On Thu, 2021-10-21 at 15:13 +0800, Chester Lin wrote:
> > Add a mmc node to support USDHC on NXP S32G2 platforms.
> >=20
> > Signed-off-by: Chester Lin <clin@suse.com>
> > ---
> > =A0arch/arm64/boot/dts/freescale/s32g2.dtsi=A0=A0=A0=A0=A0 | 32
> > +++++++++++++++++++
> > =A0.../arm64/boot/dts/freescale/s32g274a-evb.dts |=A0 4 +++
> > =A0.../boot/dts/freescale/s32g274a-rdb2.dts=A0=A0=A0=A0=A0 |=A0 4 +++
> > =A03 files changed, 40 insertions(+)
> >=20
> > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > index 59ea8a25aa4c..19e2e2561374 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > @@ -79,6 +79,26 @@ psci {
> > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0};
> > =A0=A0=A0=A0=A0=A0=A0=A0};
> > =A0
> > +=A0=A0=A0=A0=A0=A0=A0clocks {
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0usdhc_clk_module: usdhc_c=
lk_module {
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
ompatible =3D "fixed-clock";
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
lock-frequency =3D <133333333>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0#=
clock-cells =3D <0>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0};
> > +
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0usdhc_clk_ahb: usdhc_clk_=
ahb {
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
ompatible =3D "fixed-clock";
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
lock-frequency =3D <400000000>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0#=
clock-cells =3D <0>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0};
> > +
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0usdhc_clk_core: usdhc_clk=
_core {
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
ompatible =3D "fixed-clock";
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
lock-frequency =3D <400000000>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0#=
clock-cells =3D <0>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0};
>=20
> Adding the clock bindings as fixed-clock doesn't describe the hardware.
> Using fixed-clock is suitable for quartz crystals and oscillators. Here
> we should have the bindings to the clock driver. Are you planning to
> submit such driver soon or you will add here more fixed clocks every
> time you add a peripheral in the dts?
>=20

Yes, I'm planning to add real clock bindings but not just fixed rates I obs=
erved
from EVB and RDB2 boards. Since the upstream support is based on the psci
method and TF-A, I noticed that we can use SCMI clocks [+smc transport driv=
er,
e.g. "arm,scmi-smc"] as clock inputs for most IPs on S32G, and AFAICS the
downstream TF-A[1] has infrastructure to support SCMI clock protocl
[protocol-id: 0x14, arm,smc-id: 0xc20000fe].

However it will take much time to verify and upstream all SCMI-related stuf=
f
such as clock dt-bindings, so I am thinking of using fixed-clock as the fir=
st
step to have initial support before we can have all SCMI bindings get accep=
ted
by upstream.

Please feel free to let me know if any suggestions.

Regards,
Chester

[1] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/=
tree/plat/nxp/s32g/s32g_svc.c?h=3Drelease/bsp30.0-2.3

> Cheers.
> Radu P.
>=20
> > +=A0=A0=A0=A0=A0=A0=A0};
> > +
> > =A0=A0=A0=A0=A0=A0=A0=A0soc {
> > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0compatible =3D "simple-=
bus";
> > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0#address-cells =3D <1>;
> > @@ -109,6 +129,18 @@ uart2: serial@402bc000 {
> > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0status =3D "disabled";
> > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0};
> > =A0
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0usdhc0: mmc@402f0000 {
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
ompatible =3D "nxp,s32g2-usdhc";
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0r=
eg =3D <0x402f0000 0x1000>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0i=
nterrupts =3D <GIC_SPI 36
> > IRQ_TYPE_LEVEL_HIGH>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0b=
us-width =3D <8>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
locks =3D <&usdhc_clk_module>,
> > <&usdhc_clk_ahb>,
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0=A0=A0=A0=A0 <&usdhc_clk_core>;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0c=
lock-names =3D "ipg", "ahb", "per";
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0n=
o-1-8-v;
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0s=
tatus =3D "disabled";
> > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0};
> > +
> > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0gic: interrupt-controll=
er@50800000 {
> > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0compatible =3D "arm,gic-v3";
> > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0reg =3D <0x50800000 0x10000>,
> > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> > b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> > index 9118d8d2ee01..89428f1883d9 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> > +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> > @@ -32,3 +32,7 @@ memory@80000000 {
> > =A0&uart0 {
> > =A0=A0=A0=A0=A0=A0=A0=A0status =3D "okay";
> > =A0};
> > +
> > +&usdhc0 {
> > +=A0=A0=A0=A0=A0=A0=A0status =3D "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> > b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> > index e05ee854cdf5..30eae51121de 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> > +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> > @@ -38,3 +38,7 @@ &uart0 {
> > =A0&uart1 {
> > =A0=A0=A0=A0=A0=A0=A0=A0status =3D "okay";
> > =A0};
> > +
> > +&usdhc0 {
> > +=A0=A0=A0=A0=A0=A0=A0status =3D "okay";
> > +};
>=20
>=20