Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
From:   Will Deacon <will@kernel.org>
To:     Suzuki K Poulose <suzuki.poulose@arm.com>,
        mathieu.poirier@linaro.org
Cc:     catalin.marinas@arm.com, kernel-team@android.com,
        Will Deacon <will@kernel.org>, maz@kernel.org,
        leo.yan@linaro.org, coresight@lists.linaro.org,
        linux-kernel@vger.kernel.org, anshuman.khandual@arm.com,
        linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds
Date:   Thu, 21 Oct 2021 18:11:17 +0100
Message-Id: <163483495815.3806064.5821399518548380891.b4-ty@kernel.org>
In-Reply-To: <20211019163153.3692640-1-suzuki.poulose@arm.com>
References: <20211019163153.3692640-1-suzuki.poulose@arm.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 8bit
Precedence: bulk

On Tue, 19 Oct 2021 17:31:38 +0100, Suzuki K Poulose wrote:
> This series adds CPU erratum work arounds related to the self-hosted
> tracing. The list of affected errata handled in this series are :
> 
>  * TRBE may overwrite trace in FILL mode
>    - Arm Neoverse-N2	#2139208
>    - Cortex-A710	#211985
> 
> [...]

Applied first four patches to arm64 (for-next/trbe-errata), thanks!

[01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
        https://git.kernel.org/arm64/c/2d0d656700d6
[02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode
        https://git.kernel.org/arm64/c/b9d216fcef42
[03/15] arm64: errata: Add workaround for TSB flush failures
        https://git.kernel.org/arm64/c/fa82d0b4b833
[04/15] arm64: errata: Add detection for TRBE write to out-of-range
        https://git.kernel.org/arm64/c/8d81b2a38ddf

Mathieu -- feel free to pull this into the coresight tree, as I won't be
rebasing it.

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev