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[23.128.96.18]) by mx.google.com with ESMTP id bf2si7064558plb.35.2021.10.21.12.31.06; Thu, 21 Oct 2021 12:31:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=OdaRbDaP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231611AbhJUTb4 (ORCPT + 99 others); Thu, 21 Oct 2021 15:31:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230020AbhJUTbz (ORCPT ); Thu, 21 Oct 2021 15:31:55 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73276C061764 for ; Thu, 21 Oct 2021 12:29:39 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id y4so1159441plb.0 for ; Thu, 21 Oct 2021 12:29:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=1z4QCaWFWItz0HiCrhn3NpL1JJJMSCL5Ll9W/I5o9uE=; b=OdaRbDaPo2OhWmCdY0A/P9sinBvj2bsSAL7UY+BVnSUoGocUmEBff//TPbeYAkAEb+ GwghVoBbJKHWdbX3NsUMOLJGLdeT+C88zXZspyr2tMo835mpbef5zPorPPxY+gzqPo8G 5Hlv3fXGTFcDQYzHSwaYr9tIYblJeypINwS7A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=1z4QCaWFWItz0HiCrhn3NpL1JJJMSCL5Ll9W/I5o9uE=; b=EnspcouSfhcAX9wEias5fptzwv6tbezFnGHMkSEwx0mUouDtQZU7tfkL/7rzMQFNDV qAyGlJT5u8COleLDbi0XX0OQrAPt3LsKUTdG0oQV8gH8K65hHXDTCGdPg03hppAKyGYO nFuWCRBQs6DVoBONXsC33bGl4QBJ2fvoCrGxCVCSeMAeraboNMAaz2xkI3wQaueA+c+o ziXDprF4VZYOSCxGkYMBKa3M9O35AwHD5Sy3AsHWYfp79hcZ+LlnNqC9c/IaUfiyXsbd jOB1uaXn4k25YMEb/01lVTclFDGCxW/pCKB1zNJc5iXzf4O/LNhdtczwj4jxu2HUHpKI dBLQ== X-Gm-Message-State: AOAM530HhcQ/5a0tDAbL5R+F2DZ9DXAtDJiXwh4tDMIrUiTcvIGvdXjW Fs04J2NZfASwjIv/wQA+B2pVrZvuP4vcL+JF X-Received: by 2002:a17:90b:3ecb:: with SMTP id rm11mr9186152pjb.110.1634844579045; Thu, 21 Oct 2021 12:29:39 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:201:aeff:f3cb:fda2:dd71]) by smtp.gmail.com with ESMTPSA id a28sm6916262pfg.33.2021.10.21.12.29.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 12:29:38 -0700 (PDT) From: Douglas Anderson To: dri-devel@lists.freedesktop.org Cc: Philip Chen , Douglas Anderson , Boris Brezillon , Daniel Vetter , David Airlie , Jagan Teki , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , linux-kernel@vger.kernel.org Subject: [PATCH] drm/bridge: Fix the bridge chain order for pre_enable / post_disable Date: Thu, 21 Oct 2021 12:29:01 -0700 Message-Id: <20211021122719.1.I56d382006dea67ed8f30729a751fbc75434315b2@changeid> X-Mailer: git-send-email 2.33.0.1079.g6e70778dc9-goog MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Right now, the chaining order of pre_enable/enable/disable/post_disable looks like this: pre_enable: start from connector and move to encoder enable: start from encoder and move to connector disable: start from connector and move to encoder post_disable: start from encoder and move to connector In the above, it can be seen that at least pre_enable() and post_disable() are opposites of each other and enable() and disable() are opposites. However, it seems broken that pre_enable() and enable() would not move in the same direction. In other parts of Linux you can see that various stages move in the same order. For instance, during system suspend the "early" calls run in the same order as the normal calls run in the same order as the "late" calls run in the same order as the "noirq" calls. Let fix the above so that it makes more sense. Now we'll have: pre_enable: start from encoder and move to connector enable: start from encoder and move to connector disable: start from connector and move to encoder post_disable: start from connector and move to encoder This order is chosen because if there are parent-child relationships anywhere I would expect that the encoder would be a parent and the connector a child--not the other way around. This can be important when using the DP AUX bus to instantiate a panel. The DP AUX bus is likely part of a bridge driver and is a parent of the panel. We'd like the bridge to be pre_enabled before the panel and the panel to be post_disabled before the bridge. Specifically, this allows pm_runtime_put_sync_suspend() in a bridge driver's post_suspend to work properly even a panel is under it. NOTE: it's entirely possible that this change could break someone who was relying on the old order. Hopefully this isn't the case, but if this does break someone it seems like it's better to do it sonner rather than later so we can fix everyone to handle the order that makes the most sense. A FURTHER NOTE: Looking closer at commit 4e5763f03e10 ("drm/bridge: ti-sn65dsi86: Wrap panel with panel-bridge") you can see that patch inadvertently changed the order of things. The order used to be correct (panel prepare was at the tail of the bridge enable) but it became backwards. We'll restore the original order with this patch. Fixes: 4e5763f03e10 ("drm/bridge: ti-sn65dsi86: Wrap panel with panel-bridge") Fixes: 05193dc38197 ("drm/bridge: Make the bridge chain a double-linked list") Signed-off-by: Douglas Anderson --- drivers/gpu/drm/drm_bridge.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index c96847fc0ebc..98808af59afd 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -583,18 +583,14 @@ EXPORT_SYMBOL(drm_bridge_chain_mode_set); void drm_bridge_chain_pre_enable(struct drm_bridge *bridge) { struct drm_encoder *encoder; - struct drm_bridge *iter; if (!bridge) return; encoder = bridge->encoder; - list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { - if (iter->funcs->pre_enable) - iter->funcs->pre_enable(iter); - - if (iter == bridge) - break; + list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { + if (bridge->funcs->pre_enable) + bridge->funcs->pre_enable(bridge); } } EXPORT_SYMBOL(drm_bridge_chain_pre_enable); @@ -684,26 +680,30 @@ void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge, struct drm_atomic_state *old_state) { struct drm_encoder *encoder; + struct drm_bridge *iter; if (!bridge) return; encoder = bridge->encoder; - list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { - if (bridge->funcs->atomic_post_disable) { + list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { + if (iter->funcs->atomic_post_disable) { struct drm_bridge_state *old_bridge_state; old_bridge_state = drm_atomic_get_old_bridge_state(old_state, - bridge); + iter); if (WARN_ON(!old_bridge_state)) return; - bridge->funcs->atomic_post_disable(bridge, - old_bridge_state); - } else if (bridge->funcs->post_disable) { - bridge->funcs->post_disable(bridge); + iter->funcs->atomic_post_disable(iter, + old_bridge_state); + } else if (iter->funcs->post_disable) { + iter->funcs->post_disable(iter); } + + if (iter == bridge) + break; } } EXPORT_SYMBOL(drm_atomic_bridge_chain_post_disable); -- 2.33.0.1079.g6e70778dc9-goog