Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp1110450pxb; Thu, 21 Oct 2021 16:08:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxA6x5QGWZ4fFNpkHCj+snqH4XNuHE9YDMCDExRZ09UPq014eX5DwqaG+LUPdsLgKL6sBmV X-Received: by 2002:a63:1d13:: with SMTP id d19mr6570094pgd.383.1634857708819; Thu, 21 Oct 2021 16:08:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634857708; cv=none; d=google.com; s=arc-20160816; b=yT+1Yfvuzvu5pgw9gSWeC+nxJDHcSX+Tk7FrKPhbfr9iHOwx8gqUKbXHkhq+G3f3le 0G4ZJMEOS2TcYPHbsMQNaehW16/8V3KTO3jwXQRy3K2qD5ZNUntbqYQSkuV1pc8LUhFI N4J2niXHINXA9O2IixfhQtqnnGu50+hj2EuUtFk59fcQv5FA6yBGm9Je4lq+MLjedZbW z4QqVNMLCosuJS0o2p0sejcYao8szwPfWn6pZc93CJV9t0sQQp+lz+MoUG9JLo3kHL+Y OwCCKbY7f+7c05GJxy9LnN4QYKd/sGAxKE1ofdtRWnsOR7/zy8lDEMnNaJa8cuWiR/op 7iYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=llklwxb4kY0R4FgjX9hkaRkV6qqwbLLr2mY0gd19ZgI=; b=kOQKVEP/C/EClWKOo91acNwsxqUbvZVhb+ubfl7MYKwKDH9NJm01yzxNa8dPcYuaSO SwN7fnbCokqoSz+mQoKenxttPrYccfPZe/ZAnqvmaTapKB46kwdUPl/MpXBjZXBdhC74 pfcrW6mBEQ0Z2wVlsE+hda/Zlgt9Q4QcgxPLY5/x/4eqO/erwV75bSlFU09Vj6VJMd7b fBDQgOZbT2M7bsvMowWXGqB6ks7SrCdaG0CGdDuzVB++hL0bKhvx9FlB7Qed4vYjasRh SkFnwjc4xb3WEn6B33fKbQ9JgPey0axRkFb/43HDwMEfyYttlvnU1wxDxB6mlwIlFiVW d2oQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x22si302619pgj.320.2021.10.21.16.08.15; Thu, 21 Oct 2021 16:08:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232253AbhJUXHq (ORCPT + 99 others); Thu, 21 Oct 2021 19:07:46 -0400 Received: from mga05.intel.com ([192.55.52.43]:58072 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232282AbhJUXHT (ORCPT ); Thu, 21 Oct 2021 19:07:19 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10144"; a="315380060" X-IronPort-AV: E=Sophos;i="5.87,170,1631602800"; d="scan'208";a="315380060" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2021 16:02:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,170,1631602800"; d="scan'208";a="445033380" Received: from chang-linux-3.sc.intel.com ([172.25.66.175]) by orsmga006.jf.intel.com with ESMTP; 21 Oct 2021 16:02:25 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, dave.hansen@linux.intel.com, arjan@linux.intel.com, ravi.v.shankar@intel.com, chang.seok.bae@intel.com Subject: [PATCH 13/23] x86/msr-index: Add MSRs for XFD Date: Thu, 21 Oct 2021 15:55:17 -0700 Message-Id: <20211021225527.10184-14-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211021225527.10184-1-chang.seok.bae@intel.com> References: <20211021225527.10184-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org XFD introduces two MSRs: - IA32_XFD to enable/disable a feature controlled by XFD - IA32_XFD_ERR to expose the #NM trap handler which feature was tried to be used for the first time. Both use the same xstate-component bitmap format, used by XCR0. Signed-off-by: Chang S. Bae Signed-off-by: Thomas Gleixner Signed-off-by: Chang S. Bae --- arch/x86/include/asm/msr-index.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a7c413432b33..01e2650b9585 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -625,6 +625,8 @@ #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc +#define MSR_IA32_XFD 0x000001c4 +#define MSR_IA32_XFD_ERR 0x000001c5 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_APICBASE 0x0000001b -- 2.17.1