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From:   Richard Zhu <hongxing.zhu@nxp.com>
To:     Rob Herring <robh@kernel.org>
CC:     "l.stach@pengutronix.de" <l.stach@pengutronix.de>,
        "tharvey@gateworks.com" <tharvey@gateworks.com>,
        "kishon@ti.com" <kishon@ti.com>,
        "vkoul@kernel.org" <vkoul@kernel.org>,
        "galak@kernel.crashing.org" <galak@kernel.crashing.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
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        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>
Subject: RE: [PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and name
 properties
Thread-Topic: [PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and
 name properties
Thread-Index: AQHXv0hoWJtA986VIUqwmsPQQoGZiavZKzoAgAUnENA=
Date:   Fri, 22 Oct 2021 02:04:41 +0000
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> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Tuesday, October 19, 2021 3:18 AM
> To: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: l.stach@pengutronix.de; tharvey@gateworks.com; kishon@ti.com;
> vkoul@kernel.org; galak@kernel.crashing.org; shawnguo@kernel.org;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and
> name properties
>=20
> On Tue, Oct 12, 2021 at 04:41:15PM +0800, Richard Zhu wrote:
> > i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties in the
> > binding document.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index 2911e565b260..99d9863a69cd 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -128,6 +128,12 @@ properties:
> >      enum: [1, 2, 3, 4]
> >      default: 1
> >
> > +  phys:
> > +    description: Phandle of the Generic PHY to the PCIe PHY.
>=20
> maxItems: 1
>=20
> And drop 'description'
[Richard Zhu] Hi Rob:=20
Do you mean to remove all the description, and just like this?
  phys:
    maxItems: 1
Ok, got that, would be changed as this one in v4 series later.
Thanks.

Best Regards
Richard Zhu

>=20
> > +
> > +  phy-names:
> > +    const: pcie-phy
> > +
> >    reset-gpio:
> >      description: Should specify the GPIO for controlling the PCI bus
> device
> >        reset signal. It's not polarity aware and defaults to
> > active-low reset
> > --
> > 2.25.1
> >
> >