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From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Fri, 22 Oct 2021 15:55:10 +0300
Message-ID: <CAHp75VcUv6WH0--FANpRExCdEOJNVo8KCtJ2Go090=FZq-Y0UQ@mail.gmail.com>
Subject: Re: [PATCH v2 09/16] reset: starfive-jh7100: Add StarFive JH7100
 reset driver
To:     Emil Renner Berthing <kernel@esmil.dk>
Cc:     linux-riscv <linux-riscv@lists.infradead.org>,
        devicetree <devicetree@vger.kernel.org>,
        linux-clk <linux-clk@vger.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Rob Herring <robh+dt@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Linus Walleij <linus.walleij@linaro.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        Jiri Slaby <jirislaby@kernel.org>,
        Maximilian Luz <luzmaximilian@gmail.com>,
        Sagar Kadam <sagar.kadam@sifive.com>,
        Drew Fustini <drew@beagleboard.org>,
        Geert Uytterhoeven <geert@linux-m68k.org>,
        Michael Zhu <michael.zhu@starfivetech.com>,
        Fu Wei <tekkamanninja@gmail.com>,
        Anup Patel <anup.patel@wdc.com>,
        Atish Patra <atish.patra@wdc.com>,
        Matteo Croce <mcroce@microsoft.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Thu, Oct 21, 2021 at 8:43 PM Emil Renner Berthing <kernel@esmil.dk> wrote:
>
> Add a driver for the StarFive JH7100 reset controller.

...

> +config RESET_STARFIVE_JH7100
> +       bool "StarFive JH7100 Reset Driver"
> +       depends on SOC_STARFIVE || COMPILE_TEST

> +       depends on OF

No evidence of this dependency. Why to limit test coverage?

> +       default SOC_STARFIVE

...

> +/*
> + * Reset driver for the StarFive JH7100 SoC
> + *
> + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>

> + *

Redundant empty line.

> + */

...

> +#include <linux/of_device.h>

No evidence of any usage of this header. Perhaps you meant mod_devicetable.h?

...

> +static const u32 jh7100_reset_asserted[4] = {

> +       BIT(JH7100_RST_U74 % 32) |
> +       BIT(JH7100_RST_VP6_DRESET % 32) |
> +       BIT(JH7100_RST_VP6_BRESET % 32),

It's hard to notice that this is only one entry. See also below.

> +       BIT(JH7100_RST_HIFI4_DRESET % 32) |
> +       BIT(JH7100_RST_HIFI4_BRESET % 32),
> +
> +       BIT(JH7100_RST_E24 % 32)

+ Comma.

> +};

Why all these ugly % 32 against constants?

...

> +       if (!assert)
> +               done ^= mask;

Can you convert this to simple

  if (assert)
    ret = readl_...
  else
    ret = readl_...

below?

> +       spin_lock_irqsave(&data->lock, flags);
> +
> +       value = readl(reg_assert);
> +       if (assert)
> +               value |= mask;
> +       else
> +               value &= ~mask;
> +       writel(value, reg_assert);

> +       /* if the associated clock is gated, deasserting might otherwise hang forever */
> +       ret = readl_poll_timeout(reg_status, value, (value & mask) == done, 0, 1000);

You run delays under spin lock. You need to use _atomic variant.

> +       spin_unlock_irqrestore(&data->lock, flags);

...

> +       u32 value = (readl(reg_status) ^ jh7100_reset_asserted[offset]) & mask;

> +       dev_dbg(rcdev->dev, "status(%lu) = %d\n", id, !value);
> +       return !value;

Dup of ! operator. Can it be value = !(...); above?

-- 
With Best Regards,
Andy Shevchenko