Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp186764pxb; Mon, 25 Oct 2021 06:24:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwmPBXOfzq91wIbTrGwMCXnlGfbnFmTyvK7jmUihurvECdJe5cHat5IX1D8MabmWre42cR8 X-Received: by 2002:a17:90a:6388:: with SMTP id f8mr35973182pjj.141.1635168262489; Mon, 25 Oct 2021 06:24:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635168262; cv=none; d=google.com; s=arc-20160816; b=OIaiZtbD/X8pLK94ZQJQCUdKhG/H+8EI0y0IP8KnSzE2QPAM1Uo8pjhW8FSkMoGN1l OfEMERcWlqfC5NHl0J1oSVvb5+JRMPPkhqI4dksVxd+wOiLtRfz33ws8MZws8lttQwbu xAWLOAHRwySqQBEMTuhVHVZuYbKbz7cLc/WWIbYdx6rP2z/73M6eehdOKpIZDInlmZ09 XtCs0oXSyaf61cYTaH9NSXHZiLfuQz6VtgT1pcN/OfxcR7ksx6xM7THu+U0NeJTPgIOm QPgsrCLVA9wyzLCLLqCN9O7Z75Od9ohKZu4/CgyfoR+btOKp9GP14fpG4Hwj3LT3IPK2 WnAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=NjHry8Fv5zzV/JAApPjcefE7M+AQEl6U+mJvNnu7wyQ=; b=uH1EPmybkbbvQsZzbktTaSd/Cdk5JKBmsUruoqlfmz7bR09NRCfFTadFM7++R3B9xu YNpWhcFqwHwGQ++kJsgcPsPr/c8XX9wNWoKXmmq+OlXRnRhq3LGfg+qo6MkqgT0gm8Hg IjKlJikhbzGXzOHvgfDjfiJO416NdTPYUTQwKTe9sIFVSkX684xoWYjdre6fGpmi91G9 pSW+UWCMJSXvcAa5Le0Gy96vr5vcFxyj9rt2f0zoUzFl7emc/6Ds8M/POZNtWw9EiHrc Z6Fb0wKnwE222l/4F+haKFczkTL1rem1yeZBMGpwZ9dAzzoOFWGEmKbSZZTSA7tBtB87 TwmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=dFzeI9cZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b2si25823671pjl.24.2021.10.25.06.24.07; Mon, 25 Oct 2021 06:24:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=dFzeI9cZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231971AbhJYKym (ORCPT + 99 others); Mon, 25 Oct 2021 06:54:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229890AbhJYKye (ORCPT ); Mon, 25 Oct 2021 06:54:34 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7B0DC061224; Mon, 25 Oct 2021 03:52:10 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id z20so18161979edc.13; Mon, 25 Oct 2021 03:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=NjHry8Fv5zzV/JAApPjcefE7M+AQEl6U+mJvNnu7wyQ=; b=dFzeI9cZ5SddbIq480bmLmsT5M6Xll/8SFcq3UuBf1wdp8GUojw8+x0SEbwRukMVUh ALRnhxIHX6VZSIVB1copUjNOho/p5Ovbb96iZ5MA1o7ObzxZmg/a9bURhISSEIglU+A0 myBzjtbmqWBKgZ3GGZdGmM/t3fOS33lyUvrVU9nboK7WJq0gKRSQKbGsxeaAWKez2iqt FyQuG147gFRbdne++zH7gwQT0kCgQYRLYqMGivJBFk23QcMQRdvVhT2ZeTSXMlsADgaW w+te6n8Dr/kp2kro+JMpnjcjrvvPcJLuWGPj1JUo1LSfsADYHTUEfwBXz4XS7UDs7V8q mIlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NjHry8Fv5zzV/JAApPjcefE7M+AQEl6U+mJvNnu7wyQ=; b=XAMSLaVrFuEgZfXmDoAN2J0qAVw0fXcN57IKBXM/Rogfj2xNiGpds5irFUllhNPyR/ kSH0MD+T33DlbqdXdrkGSZBG/v/6ZrW9KNu6ZH1pk8wAy5SB8ANV9QSB11wqyyzZqrmU wdLbUgk4RcAsU0oPRaV7x3R0KQj+JuASpPvPdgUnDqVlG6AemamIfaI38LUAc/uKQnDr vssrq3sRi+F9mKt0uhAzrNACtkcaPLjADrUuXnQS57kXniZRHoEcF5v22riGh5Wpvnlo qeSaJthTY8LlVtgdu6nbbz4+9lGUyDytoqsPwVyDM1AIV5CflKOtRhCAj3mrR8M34+0T T2dQ== X-Gm-Message-State: AOAM531+dI0T91bwgsHBKZbGjZwmHBWKyINgevj+MfrEbznur0tO1hys 0spd2n0Rzk6eonWRFNju1oFMeFu4MPHxer4KvwA= X-Received: by 2002:a17:907:7601:: with SMTP id jx1mr21787575ejc.69.1635159129379; Mon, 25 Oct 2021 03:52:09 -0700 (PDT) MIME-Version: 1.0 References: <20211021174223.43310-1-kernel@esmil.dk> <20211021174223.43310-13-kernel@esmil.dk> In-Reply-To: From: Andy Shevchenko Date: Mon, 25 Oct 2021 13:51:15 +0300 Message-ID: Subject: Re: [PATCH v2 12/16] pinctrl: starfive: Add pinctrl driver for StarFive SoCs To: Emil Renner Berthing Cc: linux-riscv , devicetree , linux-clk , "open list:GPIO SUBSYSTEM" , "open list:SERIAL DRIVERS" , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Geert Uytterhoeven , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , Linux Kernel Mailing List , Huan Feng Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 25, 2021 at 1:24 PM Emil Renner Berthing wrote: > On Mon, 25 Oct 2021 at 12:16, Andy Shevchenko wrote: > > On Sun, Oct 24, 2021 at 12:29 PM Emil Renner Berthing wrote: > > > On Sat, 23 Oct 2021 at 23:02, Emil Renner Berthing wrote: > > > > On Sat, 23 Oct 2021 at 22:29, Andy Shevchenko wrote: > > > > > On Sat, Oct 23, 2021 at 9:46 PM Emil Renner Berthing wrote: ... > > > > > > I such cases where you get conflicting PIN_CONFIG_BIAS_* settings I > > > > > > don't see why it's better to do the rmw on the padctl register for the > > > > > > first bias setting only to then change the bits again a few > > > > > > microseconds later when the loop encounters the second bias setting. > > > > > > After the loop is done the end result would still be just the last > > > > > > bias setting. > > > > > > > > > > It could be bias X followed by something else followed by bias Y. You > > > > > will write something else with bias Y. I admit I don't know this > > > > > hardware and you and maintainers are supposed to decide what's better, > > > > > but my guts are telling me that current algo is buggy. > > > > > > > > So there is only one padctl register pr. pin. I don't see why first > > > > setting the bias bits to X, then setting some other bits, and then > > > > setting the bias bits to Y would be different from just setting all > > > > the bits in one go. Except for during that little microsecond window > > > > during the loop that I actually think it's better to avoid. > > > > > > Maybe an example is in order. Suppose we get strong pull-up, drive > > > strength 3 and pull-down config flags (the strong pull-up and pull > > > down flags conflict) and the padctl value is 0x0c0 (pull-up, input and > > > schmitt trigger enabled). With your solution of just altering the > > > padctl bits immediately we'd call starfive_padctl_rmw 3 times in rapid > > > succession like this: > > > > > > starfive_padctl_rmw(pin, 0x130, 0x100); > > > starfive_padctl_rmw(pin, 0x007, 0x003); > > > starfive_padctl_rmw(pin, 0x130, 0x010); > > > > > > ..and the end result would be 0x0d3, although the strong pull-up would > > > be enabled for the microseconds between the 1st and 3nd call. > > > As the code is now it'd just directly do > > > > > > starfive_padctl_rmw(pin, 0x137, 0x013) > > > > > > ..which again results in 0x0d3, only without the microsecond blink of > > > the strong pull-up. > > > > You missed the point. Hardware on the other end may behave well > > differently in these two cases. > > Right, but that can never be an intended behaviour. Which of the > conflicting bias settings comes first and is blipped before the 2nd > remains entirely depends on how the pinctrl framework parses the > devicetree. I'd much rather have it cleanly go to just one of the > states, which might be the wrong one, but the conflicting bias > settings are wrong to begin with. That's why I said that is up to you and maintainers and people who know hardware better than me. -- With Best Regards, Andy Shevchenko