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[24.6.216.183]) by smtp.gmail.com with ESMTPSA id b6sm22238132pfv.171.2021.10.25.09.42.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 25 Oct 2021 09:42:20 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [PATCH v2 0/5] mm/mprotect: avoid unnecessary TLB flushes From: Nadav Amit In-Reply-To: Date: Mon, 25 Oct 2021 09:42:19 -0700 Cc: Andrew Morton , Linux-MM , LKML , Andi Kleen , Andrea Arcangeli , Andrew Cooper , Andy Lutomirski , Dave Hansen , Peter Xu , Thomas Gleixner , Will Deacon , Yu Zhao , Nick Piggin , x86@kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <20211021122112.592634-1-namit@vmware.com> <20211021200450.b13499c379a27dbfefe9f5e3@linux-foundation.org> To: Peter Zijlstra X-Mailer: Apple Mail (2.3654.120.0.1.13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Oct 25, 2021, at 3:50 AM, Peter Zijlstra = wrote: >=20 > On Thu, Oct 21, 2021 at 08:04:50PM -0700, Andrew Morton wrote: >> On Thu, 21 Oct 2021 05:21:07 -0700 Nadav Amit = wrote: >>=20 >>> This patch-set is intended to remove unnecessary TLB flushes. It is >>> based on feedback from v1 and several bugs I found in v1 myself. >>>=20 >>> Basically, there are 3 optimizations in this patch-set: >>> 1. Avoiding TLB flushes on change_huge_pmd() that are only needed to >>> prevent the A/D bits from changing. >>> 2. Use TLB batching infrastructure to batch flushes across VMAs and >>> do better/fewer flushes. >>> 3. Avoid TLB flushes on permission demotion. >>>=20 >>> Andrea asked for the aforementioned (2) to come after (3), but this >>> is not simple (specifically since change_prot_numa() needs the = number >>> of pages affected). >>=20 >> [1/5] appears to be a significant fix which should probably be >> backported into -stable kernels. If you agree with this then I = suggest >> it be prepared as a standalone patch, separate from the other four >> patches. With a cc:stable. >=20 > I am confused, 1/5 doesn't actually do *anything*. I also cannot find > any further usage of the introduced X86_BUG_PTE_LEAK. >=20 > I'm thinking patch #2 means to have something like: >=20 > if (cpu_feature_enabled(X86_BUG_PTE_LEAK)) > flush_pmd_tlb_range(vma, address, address + = HPAGE_PMD_SIZE); >=20 > In the newly minted: pmdp_invalidate_ad(), but alas, nothing there. This change was only intended for pmdp_invalidate_ad() but somehow got lost. I will add it there. I eventually did not add the optimization to avoid TLB flushes on (!dirty|write)->!write so I did not use it for the first case that you mentioned. I am too afraid, although I think this is correct. Perhaps I will add it as a separate patch.