Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp103955pxb; Tue, 26 Oct 2021 22:30:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvls7wkE7HRDkKTjbkAGLJLuW1GzGLmxhrGnuO+75d8XpIkdRXJYcaBo0kvpNXISB6DWRo X-Received: by 2002:a63:950f:: with SMTP id p15mr22444389pgd.265.1635312629851; Tue, 26 Oct 2021 22:30:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635312629; cv=none; d=google.com; s=arc-20160816; b=F5nJcKhLTT4TqoC550TEMDfuQQQCvVLAtr6b3bKciJqkJHVZP0vTwowWJQjLkpRqQH 8/3A1rL9GSunYiNcL3tFkO4EeiIJ/Jf+ROxz2Ikj/gCdMg2DnyPHPF/+F7+1bE/KLERY s3kPTxr/OCzzviAWJrb+HKz9nVYL7tWvrGMewcdPXYTGYQysa5salwRkhyYbRcbJsjrP jZzixONbP/SX6ApkwV+lFKqDEc6okxH5+Qd3HnvZyY3DSvdKAGvOKYoAPOSjZ8AbFydo XJHfW8yFfmJWcpsXvJg+18Hwzp2RBWsQBPn7eaKZ6XIranszR4ZAGVzvlDjIhatV4e/W o2Ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=6RL28FsvtQQ1VCoOvXApATqii1tMJtUVbIdxzS4Kq9E=; b=rxUFuVEoGv8Vj+uYkAKJfwH0R4jwoAvUn5kuFDcPlhFMAt+S7ovoeI7SBQvAKscSNy I/UlQTmsUCgVvY1bJNUhIEo+sb5mMYqBJNAOfAmxmW8RCJb5+ZCV9tX80yxstrPuoxQQ I8MfJVpffWNmtJqA9LY7YYz0oNFh/snpwVfTqFifgxyNOsaZo1AKY5y4qy+RiqvrngXx LKSJLZVHlbY1IaXCR5HeIIGDYJeC7fp896DvgkTTqj+zSJr5dgxPGLK69WPNsVsmVKTa ZjYRDgF1ubmq9dcV/8NlsdlOcSkXKoBmtaEwqe3eE0gt2c6UlkfXvhSsBsX/AgbUyQdI 4Wlg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w6si10564685pgh.46.2021.10.26.22.30.16; Tue, 26 Oct 2021 22:30:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238006AbhJZSPv (ORCPT + 99 others); Tue, 26 Oct 2021 14:15:51 -0400 Received: from aposti.net ([89.234.176.197]:40374 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238118AbhJZSPu (ORCPT ); Tue, 26 Oct 2021 14:15:50 -0400 From: Paul Cercueil To: David Airlie , Daniel Vetter Cc: Laurent Pinchart , Sam Ravnborg , "H . Nikolaus Schaller" , Paul Boddie , list@opendingux.net, linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [RESEND PATCH v3 4/6] drm/ingenic: Set DMA descriptor chain register when starting CRTC Date: Tue, 26 Oct 2021 19:12:38 +0100 Message-Id: <20211026181240.213806-5-paul@crapouillou.net> In-Reply-To: <20211026181240.213806-1-paul@crapouillou.net> References: <20211026181240.213806-1-paul@crapouillou.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Setting the DMA descriptor chain register in the probe function has been fine until now, because we only ever had one descriptor per foreground. As the driver will soon have real descriptor chains, and the DMA descriptor chain register updates itself to point to the current descriptor being processed, this register needs to be reset after a full modeset to point to the first descriptor of the chain. Signed-off-by: Paul Cercueil --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 5dbeca0f8f37..cbc76cede99e 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -186,6 +186,10 @@ static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, regmap_write(priv->map, JZ_REG_LCD_STATE, 0); + /* Set address of our DMA descriptor chain */ + regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, 0)); + regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_ENABLE); -- 2.33.0