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Date:   Tue, 26 Oct 2021 17:12:56 -0700 (PDT)
Subject:     Re: [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports
In-Reply-To: <20211025040607.92786-1-wefu@redhat.com>
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From:   Palmer Dabbelt <palmerdabbelt@google.com>
To:     wefu@redhat.com
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On Sun, 24 Oct 2021 21:06:05 PDT (-0700), wefu@redhat.com wrote:
> From: Fu Wei <wefu@redhat.com>
>
> This patch follows the  RISC-V standard Svpbmt extension in
> privilege spec to solve the non-coherent SOC DMA synchronization
> issues.
>
> The svpbmt PTE format:
> | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
>   N     MT     RSW    D   A   G   U   X   W   R   V
>         ^
>
> Of the Reserved bits [63:54] in a leaf PTE, the bits [62:61] are used as
> the MT (aka MemType) field. This field specifies one of three memory types
> as shown in the following table：
> MemType     RISC-V Description
> ----------  ------------------------------------------------
> 00 - PMA    Normal Cacheable, No change to implied PMA memory type
> 01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
> 10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
> 11 - Rsvd   Reserved for future standard use

Do you have a pointer to the spec that contains these?  I'm specifically
worried about these page-based attributes being elided when paging is
off (ie, M-mode), which has caused issues in systems I've worked with in
the past.  I'm assuming there's something related to this in the specs,
but I'm worried we'll need some sort of ack from M-mode that it's been
setup to work that way.  One could imagine an MPRV-like approach 
working, but I don't see enough in the old specs and I'm having trouble 
figuring out where the canonical version of this lives.

> The standard protection_map[] needn't be modified because the "PMA"
> type keeps the highest bits zero.
> And the whole modification is limited in the arch/riscv/* and using
> a global variable(__riscv_svpbmt) as _PAGE_DMA_MASK/IO/NC for
> pgprot_noncached (&writecombine) in pgtable.h.
> We also add _PAGE_CHG_MASK to filter PFN than before.
>
> Enable it in devicetree - (Add "mmu-supports-svpbmt" in cpu node)
>  - mmu-supports-svpbmt

Maybe this is enough of an ack, but we'll need to have some pretty
specific documentation if that's the case.  It's not described that way 
in the docs right now, they just talk about CPU support (IMO we could 
probe that with a trap, but I'm fine with the DT entry as it's a bit 
simpler).

> Wei Fu (2):
>   dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt
>   riscv: add RISC-V Svpbmt extension supports
>
>  .../devicetree/bindings/riscv/cpus.yaml       |  5 +++
>  arch/riscv/include/asm/fixmap.h               |  2 +-
>  arch/riscv/include/asm/pgtable-64.h           |  8 ++--
>  arch/riscv/include/asm/pgtable-bits.h         | 41 ++++++++++++++++++-
>  arch/riscv/include/asm/pgtable.h              | 39 ++++++++++++++----
>  arch/riscv/kernel/cpufeature.c                | 32 +++++++++++++++
>  arch/riscv/mm/init.c                          |  5 +++
>  7 files changed, 117 insertions(+), 15 deletions(-)