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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8676.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 15c385b9-7fff-4b60-8c88-08d998ea949a X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Oct 2021 01:39:13.1426 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: R9oCygYlqNrGytRFlSugceXAdQEjrQ6jQI8OQDc9fYGDiYEp9ucWT6aF2ZDMTay9FayvRt64wEtCSORSoqyakw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8484 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Marcel Ziswiler > Sent: Tuesday, October 26, 2021 11:57 PM > To: kishon@ti.com; vkoul@kernel.org; robh@kernel.org; > l.stach@pengutronix.de; shawnguo@kernel.org; tharvey@gateworks.com; > galak@kernel.crashing.org; Richard Zhu > Cc: linux-phy@lists.infradead.org; linux-arm-kernel@lists.infradead.org; > kernel@pengutronix.de; devicetree@vger.kernel.org; > linux-kernel@vger.kernel.org; dl-linux-imx > Subject: Re: [PATCH v3 0/9] add the imx8m pcie phy driver and imx8mm pcie > support >=20 > On Tue, 2021-10-12 at 16:41 +0800, Richard Zhu wrote: > > refer to the discussion [1] when try to enable i.MX8MM PCIe support, > > one standalone PCIe PHY driver should be seperated from i.MX PCIe > > driver when enable i.MX8MM PCIe support. > > > > This patch-set adds the standalone PCIe PHY driver suport[1-5], and > > i.MX8MM PCIe support[6-9] to have whole view to review this patch-set. > > > > The PCIe works on i.MX8MM EVK board based the the blkctrl power driver > > [2] and this PHY driver patch-set. >=20 > Whole series: >=20 > Tested-by: Marcel Ziswiler >=20 > BTW: I tested it on Verdin iMX8M Mini V1.1B without an external PCIe > oscillator aka setting fsl,refclk-pad-mode to > IMX8_PCIE_REFCLK_PAD_OUTPUT which worked like a charm. Thanks! >=20 [Richard Zhu] Thanks for your tests. Best Regards Richard Zhu > > [1] > > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fpat= c > > > hwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F20210510141509.929 > 120 > > > -3-l.stach%40pengutronix.de%2F&data=3D04%7C01%7Chongxing.zhu%40 > nxp.c > > > om%7Cbacb5db20f2d4aa7a4ad08d998993356%7C686ea1d3bc2b4c6fa92cd9 > 9c5c3016 > > > 35%7C0%7C0%7C637708606037565160%7CUnknown%7CTWFpbGZsb3d8ey > JWIjoiMC4wLj > > > AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000& > ;sdata=3D > > > Mmea0v4pP5VzSM%2F8sIStLkwvA0pY0h2lG4Vzvr8Gk%2F4%3D&reserv > ed=3D0 > > [2] > > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fpat= c > > > hwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fcover%2F202109102026 > 40 > > .980366-1-l.stach%40pengutronix.de%2F&data=3D04%7C01%7Chongxin > g.zhu% > > > 40nxp.com%7Cbacb5db20f2d4aa7a4ad08d998993356%7C686ea1d3bc2b4c6 > fa92cd99 > > > c5c301635%7C0%7C0%7C637708606037565160%7CUnknown%7CTWFpbGZ > sb3d8eyJWIjo > > > iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C10 > 00& > > ;sdata=3D5U%2BP0zL0OskhyB0RtH%2FsBwRn0B1Lb27ZSpjjhFD0wUo%3D&a > mp;reserved > > =3D0 > > > > Main changes v2 --> v3: > > - Regarding Lucas' comments. > > =A0- to have a whole view to review the patches, send out the i.MX8MM > PCIe support too. > > =A0- move the PHY related bits manipulations of the GPR/SRC to standalo= ne > PHY driver. > > =A0- split the dts changes to SOC and board DT, and use the enum instea= d of > raw value. > > =A0- update the license of the dt-binding header file. > > > > Changes v1 --> v2: > > - Update the license of the dt-binding header file to make the license > > =A0 compatible with dts files. > > - Fix the dt_binding_check errors. > > > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml=A0=A0=A0 |=A0= =A0 6 > +++ > > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |=A0 79 > > +++++++++++++++++++++++++++++ > > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0 | > 53 > > ++++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mm.dtsi > > |=A0 46 ++++++++++++++++- > drivers/pci/controller/dwc/pci-imx6.c > > |=A0 63 ++++++++++++++++++++++- > drivers/phy/freescale/Kconfig > > |=A0=A0 9 ++++ > drivers/phy/freescale/Makefile > > |=A0=A0 1 + > drivers/phy/freescale/phy-fsl-imx8m-pcie.c=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0 | > > 218 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++ > > > include/dt-bindings/phy/phy-imx8-pcie.h=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 | > 14 > > ++++++ > > 9 files changed, 486 insertions(+), 3 deletions(-) > > > > [PATCH v3 1/9] dt-bindings: phy: phy-imx8-pcie: Add binding for the > > [PATCH v3 2/9] dt-bindings: phy: add imx8 pcie phy driver support > > [PATCH v3 3/9] arm64: dts: imx8mm: add the pcie phy support [PATCH v3 > > 4/9] arm64: dts: imx8mm-evk: add the pcie phy support [PATCH v3 5/9] > > phy: freescale: pcie: initialize the imx8 pcie [PATCH v3 6/9] > > dt-bindings: imx6q-pcie: Add PHY phandles and name [PATCH v3 7/9] > > arm64: dts: imx8mm: add the pcie support [PATCH v3 8/9] arm64: dts: > > imx8mm-evk: add the pcie support on imx8mm [PATCH v3 9/9] PCI: imx: > > add the imx8mm pcie support