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[209.85.166.173]) by smtp.gmail.com with ESMTPSA id y5sm2796759ilv.5.2021.10.27.02.32.25 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Oct 2021 02:32:26 -0700 (PDT) Received: by mail-il1-f173.google.com with SMTP id j3so2252283ilr.6 for ; Wed, 27 Oct 2021 02:32:25 -0700 (PDT) X-Received: by 2002:a05:6e02:1747:: with SMTP id y7mr18329876ill.95.1635327145411; Wed, 27 Oct 2021 02:32:25 -0700 (PDT) MIME-Version: 1.0 References: <20211027021857.20816-1-jason-jh.lin@mediatek.com> <20211027021857.20816-4-jason-jh.lin@mediatek.com> In-Reply-To: <20211027021857.20816-4-jason-jh.lin@mediatek.com> From: Fei Shao Date: Wed, 27 Oct 2021 17:31:49 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 3/6] drm/mediatek: Detect CMDQ execution timeout To: "jason-jh.lin" Cc: Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , Jassi Brar , Yongqiang Niu , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hsinyi@chromium.org, nancy.lin@mediatek.com, singo.chang@mediatek.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jason, On Wed, Oct 27, 2021 at 10:19 AM jason-jh.lin wrote: > > From: Chun-Kuang Hu > > CMDQ is used to update display register in vblank period, so > it should be execute in next 2 vblank. One vblank interrupt > before send message (occasionally) and one vblank interrupt > after cmdq done. If it fail to execute in next 3 vblank, > tiemout happen. > > Signed-off-by: Chun-Kuang Hu > Signed-off-by: jason-jh.lin > Reviewed-by: Chun-Kuang Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index e23e3224ac67..dad1f85ee315 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -54,6 +54,7 @@ struct mtk_drm_crtc { > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > struct cmdq_client cmdq_client; > u32 cmdq_event; > + u32 cmdq_vblank_cnt; > #endif > > struct device *mmsys_dev; > @@ -227,7 +228,10 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, > static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) > { > struct cmdq_cb_data *data = mssg; > + struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client); > + struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client); > > + mtk_crtc->cmdq_vblank_cnt = 0; > cmdq_pkt_destroy(data->pkt); > } > #endif > @@ -483,6 +487,15 @@ static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, > cmdq_handle->pa_base, > cmdq_handle->cmd_buf_size, > DMA_TO_DEVICE); > + /* > + * CMDQ command should execute in next 3 vblank. > + * One vblank interrupt before send message (occasionally) > + * and one vblank interrupt after cmdq done, > + * so it's timeout after 3 vblank interrupt. > + * If it fail to execute in next 3 vblank, timeout happen. > + */ > + mtk_crtc->cmdq_vblank_cnt = 3; > + > mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); > mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); > } > @@ -499,11 +512,14 @@ static void mtk_crtc_ddp_irq(void *data) > > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) > + mtk_crtc_ddp_config(crtc, NULL); > + else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) I think atomic_dec_and_test() does what you want to do here. > + DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", > + drm_crtc_index(&mtk_crtc->base)); > #else > if (!priv->data->shadow_register) > -#endif > mtk_crtc_ddp_config(crtc, NULL); > - > +#endif > mtk_drm_finish_page_flip(mtk_crtc); > } > > -- > 2.18.0 >