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[23.128.96.18]) by mx.google.com with ESMTP id x3si1346761pgr.434.2021.10.27.14.25.21; Wed, 27 Oct 2021 14:25:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=StFhjxBA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237073AbhJ0NgW (ORCPT + 97 others); Wed, 27 Oct 2021 09:36:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237213AbhJ0NgV (ORCPT ); Wed, 27 Oct 2021 09:36:21 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C54FC061767 for ; Wed, 27 Oct 2021 06:33:55 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id u5so4717978ljo.8 for ; Wed, 27 Oct 2021 06:33:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=SF3TuLDwjCSTuZKZbIAlHelYHC/Il4xa/tsPH6DiGEk=; b=StFhjxBA3IYeh9xk7RxqepC2BTyp6miu58c8IkRnymFpoS65OAATRBs7/kyVTuxoGw gu/PqDKU65tuETTCV7BjhfDevG+pkJFpVNaRwfjzs3g1oQR3HXznUf7LGudjcpuOjea1 p4cSk9qhmET+0GBnNbq2t0+UR83tD//Q8k5H5MppGhwBLdLyMNYxz2J8v0pye1w6UBXf uNLYDPTBI6AtB92nh+JyboY5Bd4wjk0OCPWJr5vsktR5/ugKhipEXjTdyO6nPO29IET/ 0UFJ4Gsj/mrHYibEAq580ICfQxLt1PwnbkxeVasgzNRRvxcdLnweWv8kODSF7FTvGMAs jQZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=SF3TuLDwjCSTuZKZbIAlHelYHC/Il4xa/tsPH6DiGEk=; b=GiO9ubhZgy13dOA6S7q+TRy9fnNenNPl9WC32kevY7hVYl+vGcruv360LiFulktYak JWAMIsERLPCO/HNDjMsgRrqNm7D4GGHl9Swk8Uth5rl40yRECDTMjxK7VhE2WiOUuLcD QEiXoqh3vrpL9yg1Q0+scBzkZ9X0V54Ds1045yAokpX6GSUIqpTMXdJObwxkgDscvjNx 9UZ+o2TS9a+5xlxxZJkkxFHigQixQJ08gAUnyPzIN+skgDBbgRStO/L/ZiHhiou13Abu gzk+CIfEGo4zFUl/TQYMoN1NHT7ZdvxhVmsybkrbULhv0/hYzL6nrJBKnO5fRmD13DvR mdaQ== X-Gm-Message-State: AOAM531adUh2igAWtuiYFEs6B/YbLJD5hsygEvaYvgBji7mNWwU2L9nN 0rneGk75aK8i6JycxiXRQcETu/Co0zPj6wrMK/kQIQ== X-Received: by 2002:a2e:85c4:: with SMTP id h4mr33373312ljj.4.1635341633803; Wed, 27 Oct 2021 06:33:53 -0700 (PDT) MIME-Version: 1.0 References: <20211027115516.4475-1-rashmi.a@intel.com> In-Reply-To: <20211027115516.4475-1-rashmi.a@intel.com> From: Ulf Hansson Date: Wed, 27 Oct 2021 15:33:17 +0200 Message-ID: Subject: Re: [RESEND PATCH v2 0/4] Add support of eMMC PHY for Intel Thunder To: rashmi.a@intel.com Cc: michal.simek@xilinx.com, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kishon@ti.com, vkoul@kernel.org, andriy.shevchenko@linux.intel.com, linux-phy@lists.infradead.org, mgross@linux.intel.com, kris.pan@linux.intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, adrian.hunter@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 27 Oct 2021 at 13:55, wrote: > > From: Rashmi A > > This patch set enables the support for eMMC PHY on the Intel Thunder > Bay SoC. eMMC PHY is based on arasan phy. > > Patch 1 Adds arasan sdhci support for eMMC in Intel Thunder Bay. > Patch 2 Adds arasan sdhci dt bindings. > Patch 3 Holds the device tree binding documentation for eMMC PHY > and listings of new files in MAINTAINERS file. > Patch 4 Holds the eMMC PHY driver. > > Reseding V2 patchset to get the dt-binding patches reviewed. I have already queued patch1 and patch2, so there is no need to resend them anymore. Kind regards Uffe > > Changes from v1: > Add arasan sdhci dt bindings > > Rashmi A (4): > mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan > eMMC driver > dt-bindings: mmc: Add bindings for Intel Thunder Bay SoC > dt-bindings: phy: intel: Add Thunder Bay eMMC PHY bindings > phy: intel: Add Thunder Bay eMMC PHY support > > .../devicetree/bindings/mmc/arasan,sdhci.yaml | 25 + > .../phy/intel,phy-thunderbay-emmc.yaml | 46 ++ > MAINTAINERS | 7 + > drivers/mmc/host/sdhci-of-arasan.c | 29 +- > drivers/phy/intel/Kconfig | 10 + > drivers/phy/intel/Makefile | 1 + > drivers/phy/intel/phy-intel-thunderbay-emmc.c | 511 ++++++++++++++++++ > 7 files changed, 628 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml > create mode 100644 drivers/phy/intel/phy-intel-thunderbay-emmc.c > > -- > 2.17.1 >