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Message-ID: <f18b283f-67b2-6847-036b-e27cc5a327db@gmail.com>
Date:   Wed, 27 Oct 2021 22:28:33 +0200
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Subject: Re: [PATCH] ARM: dts: BCM5301X: Fix I2C controller interrupt
To:     Florian Fainelli <f.fainelli@gmail.com>,
        linux-arm-kernel@lists.infradead.org
Cc:     chunkeey@gmail.com, mnhagan88@gmail.com,
        Hauke Mehrtens <hauke@hauke-m.de>,
        "maintainer:BROADCOM BCM5301X ARM ARCHITECTURE" 
        <bcm-kernel-feedback-list@broadcom.com>,
        Rob Herring <robh+dt@kernel.org>,
        Jon Mason <jonmason@broadcom.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>
References: <20211027193730.3941945-1-f.fainelli@gmail.com>
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On 27.10.2021 21:37, Florian Fainelli wrote:
> The I2C interrupt controller line is off by 32 because the datasheet
> describes interrupt inputs into the GIC which are for Shared Peripheral
> Interrupts and are starting at offset 32. The ARM GIC binding expects
> the SPI interrupts to be numbered from 0 relative to the SPI base.
> 
> Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

Thanks for fixing that. I don't have any device utilzing I2C and so
never notice that issue.