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Date:   Wed, 27 Oct 2021 14:22:24 -0700 (PDT)
Subject:     Re: [PATCH] riscv: fix misalgned trap vector base address
In-Reply-To: <20211018052238.522905-1-181250012@smail.nju.edu.cn>
CC:     Paul Walmsley <paul.walmsley@sifive.com>, aou@eecs.berkeley.edu,
        alex@ghiti.fr, vitaly.wool@konsulko.com, anup@brainfault.org,
        seanga2@gmail.com, wangkefeng.wang@huawei.com,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        yuzihao@ict.ac.cn, 181250012@smail.nju.edu.cn
From:   Palmer Dabbelt <palmer@dabbelt.com>
To:     181250012@smail.nju.edu.cn
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On Sun, 17 Oct 2021 22:22:38 PDT (-0700), 181250012@smail.nju.edu.cn wrote:
> * The trap vector marked by label .Lsecondary_park should align on a
>   4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
>   and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
>
> Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
> ---
>  arch/riscv/kernel/head.S | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
>  	csrw CSR_SCRATCH, zero
>  	ret
>
> +.align 2
>  .Lsecondary_park:
>  	/* We lack SMP support or have too many harts, so park this hart */
>  	wfi

Thanks, this is on fixes (with some commit message cleanups).