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[23.128.96.18]) by mx.google.com with ESMTP id q11si1322983edj.26.2021.10.27.14.58.17; Wed, 27 Oct 2021 14:58:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I5SHd85j; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240904AbhJ0IeK (ORCPT + 99 others); Wed, 27 Oct 2021 04:34:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240936AbhJ0Id5 (ORCPT ); Wed, 27 Oct 2021 04:33:57 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 469F1C0432C1 for ; Wed, 27 Oct 2021 01:29:20 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id d9so2021021pfl.6 for ; Wed, 27 Oct 2021 01:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=thzDWFk9Q0tPB9sJfYt3NFAW2DK3VreaLCq6cyyRMEE=; b=I5SHd85j9XYMXkGN3HPiKAs3OiCmon5wOEaUYkYPQEJRzcAsr/i815L/DDBTmgAZlK EFp67Jm8jst08kO5YrOlU+k8GkQao+bnmNngHPVii4coZ9DKOPIusqOBSszH1FXQqkWW y8arffbFWprqCu3qQ1fUVff5XmPh1QZ5FP4h/8MjNw91DQZeEAqclM0AaRugzY9O42st Q018apx9bqf2Y817pghf4orHBr0Qd9HVokKGyqXtr1/sJEtTpAXmPDxYl6jqAEICOz3g e89gnZpZjW009WCkYivSwwYbqiz4+RZpXKx6ZT0FSJhL3HFv+ZXsXGu9GwIDQkxv3zP5 f4Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=thzDWFk9Q0tPB9sJfYt3NFAW2DK3VreaLCq6cyyRMEE=; b=W6og1bDrDAt38mjDw6SCGPXrKQc2p5yAKeoEEbWG5BmJJpu6EtLNF8mx+pAiFVtUbQ jQ1XI4FmfC7Lf2FDlS/J3GO+MejOPSPhZi4u30zwBX5nzj6pJ6gsu7h46WRZqLazep/i AQNEtU38L9u0X5tqOTnHusvVuRXt/sCVDDTjbQLm7fF1pchBC02pF6Y59ooXNN+flQas fGvIs/SNQpDrnxPnmyWuQltb20VGwQvVFNEveAIWra4HI+Q60s1xDi3xR8ranmRQ4klw FtllRYg7nhSOHieN/22RvURx1Wkf0Iill29EsbwzKXOfPg29zanD8MwYLdvcYulcyRhn eoew== X-Gm-Message-State: AOAM530g2FT+GRoiTxOrs4dTtTyUUBelMVn7vlTIE3arw9sVmV/0hka5 Y0fYyfD98B1r9GGJApviFwY4dFyT9H2KFfzMgn/2TQ== X-Received: by 2002:a62:dd96:0:b0:47c:1b37:d0f with SMTP id w144-20020a62dd96000000b0047c1b370d0fmr7148072pff.1.1635323359684; Wed, 27 Oct 2021 01:29:19 -0700 (PDT) MIME-Version: 1.0 References: <20211025170925.3096444-1-bjorn.andersson@linaro.org> <20211025170925.3096444-2-bjorn.andersson@linaro.org> In-Reply-To: <20211025170925.3096444-2-bjorn.andersson@linaro.org> From: Robert Foss Date: Wed, 27 Oct 2021 10:29:08 +0200 Message-ID: Subject: Re: [PATCH v7 2/3] drm/bridge: ti-sn65dsi86: Use regmap_bulk_write API To: Bjorn Andersson Cc: Thierry Reding , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Lee Jones , linux-pwm@vger.kernel.org, linux-kernel , MSM Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hey Bjorn, On Mon, 25 Oct 2021 at 19:07, Bjorn Andersson wrote: > > The multi-register u16 write operation can use regmap_bulk_write() > instead of two separate regmap_write() calls. > > It's uncertain if this has any effect on the actual updates of the > underlying registers, but this at least gives the hardware the > opportunity and saves us one transation on the bus. > > Signed-off-by: Bjorn Andersson Did you miss including Dougs R-B from v6? As far as I can tell nothing else changed between v6 & v7. > --- > > Changes since v6: > - None > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index 6154bed0af5b..5b59d8dd3acd 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -193,8 +193,9 @@ static const struct regmap_config ti_sn65dsi86_regmap_config = { > static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, > unsigned int reg, u16 val) > { > - regmap_write(pdata->regmap, reg, val & 0xFF); > - regmap_write(pdata->regmap, reg + 1, val >> 8); > + u8 buf[2] = { val & 0xff, val >> 8 }; > + > + regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); > } > > static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata) > -- > 2.29.2 >