Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp1303419pxb; Thu, 28 Oct 2021 00:54:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/P3RZDF2jO+52BGTXVlOldNYo7uWgY85RiKQi/uFYT3u5gxKv9jPJKBIEvWFwLHVlbcn2 X-Received: by 2002:aa7:8b56:0:b0:44c:10a:4ee9 with SMTP id i22-20020aa78b56000000b0044c010a4ee9mr2758127pfd.46.1635407672535; Thu, 28 Oct 2021 00:54:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635407672; cv=none; d=google.com; s=arc-20160816; b=rKPP+0awBIAvFr0BOcU3DYvGL8HC2w0514cuLPQtwrFdZK3YJkMsi1de4BE/Ld7ybT iA4DwsUCWYYQcby1vQs3HIu4YBX3vkNmNu5qPlK1ICUr6jgG2Q5Xj99YHY5C/8+L6qjU qV52hNYDv/lDEX6YTh8nL6zGkm9lu+C0JAYQsvycSRduI8hZ/w2ugs8XUFjG3IigdCf3 QouOSQ18xQcqMFn38/bwf017jIQff1q1lgL2JGM/P7ZTH3yLDNhmcbMXoXgO6UjlA5DT W7nUyKnEaICOshZdQ4x4yfwr/ByE8aM7c1ZX9H63QVy4/T498kA7BaARb3CcR4tWCT1d eFRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=HHS6H8Sn6qoU6gnvgGupYUH5XOI8/ATzgQ4LROdnaRE=; b=ZkmcWX9AnPbteO/P+dqOgXLptpoiEHW8uVweetQllaPJh3AsiLCnODfSLyc/5Rtdrf CqPEH6ORg747RPOAHmW1RVz92jSQ0nqikI8SQEMT5wq8HaXdZ4P7F2KNFTcp8Nf48a2Z coTUq9rnLJupR362Uw+gg8i6rYrbWAXSylCbp3+Bxph4pMv34kYkN2kKrXHyVy6fNIiI JC4gAp2kwPVQ6lmv122mf0XyULBB6c65x6zqKd7aFdBh0Z+o/o+3XADIntYg3klkEIQ+ 9hZHp46MT83WjQGzKPCNGp8rO7Nfit9pnYWNooQDcFKcdoEFL3Q59OJQD6/prRnhqM4+ aJBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r17si2811111pgh.182.2021.10.28.00.54.20; Thu, 28 Oct 2021 00:54:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230080AbhJ1Hze (ORCPT + 99 others); Thu, 28 Oct 2021 03:55:34 -0400 Received: from inva021.nxp.com ([92.121.34.21]:33038 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229993AbhJ1Hzc (ORCPT ); Thu, 28 Oct 2021 03:55:32 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 54298200399; Thu, 28 Oct 2021 09:53:05 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 1BFD9200388; Thu, 28 Oct 2021 09:53:05 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 87820183AC8B; Thu, 28 Oct 2021 15:53:02 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, kishon@ti.com, vkoul@kernel.org, robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Richard Zhu Subject: [PATCH v4 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name properties Date: Thu, 28 Oct 2021 15:27:12 +0800 Message-Id: <1635406037-20900-4-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1635406037-20900-1-git-send-email-hongxing.zhu@nxp.com> References: <1635406037-20900-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties in the binding document. Signed-off-by: Richard Zhu Tested-by: Marcel Ziswiler --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 2911e565b260..46b5446f5791 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -128,6 +128,12 @@ properties: enum: [1, 2, 3, 4] default: 1 + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + reset-gpio: description: Should specify the GPIO for controlling the PCI bus device reset signal. It's not polarity aware and defaults to active-low reset -- 2.25.1