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Date:   Thu, 28 Oct 2021 13:55:23 +0300
From:   Nikita Shubin <nikita.shubin@maquefel.me>
To:     Marc Zyngier <maz@kernel.org>
Cc:     guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
        tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de,
        robh@kernel.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org, Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic
 request_threaded_irq with ONESHOT
Message-ID: <20211028135523.5cf4b66b@redslave.neermore.group>
In-Reply-To: <87a6ixbcse.wl-maz@kernel.org>
References: <20211024013303.3499461-1-guoren@kernel.org>
        <20211024013303.3499461-4-guoren@kernel.org>
        <87a6ixbcse.wl-maz@kernel.org>
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Hello Marc and Guo Ren!

On Mon, 25 Oct 2021 11:48:33 +0100
Marc Zyngier <maz@kernel.org> wrote:

> On Sun, 24 Oct 2021 02:33:03 +0100,
> guoren@kernel.org wrote:
> > 
> > From: Guo Ren <guoren@linux.alibaba.com>
> > 
> > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the
> > driver, only the first interrupt could be handled, and continue irq
> > is blocked by hw. Because the thead,c900-plic couldn't complete
> > masked irq source which has been disabled in enable register. Add
> > thead_plic_chip which fix up c906-plic irq source completion
> > problem by unmask/mask wrapper.
> > 
> > Here is the description of Interrupt Completion in PLIC spec [1]:
> > 
> > The PLIC signals it has completed executing an interrupt handler by
> > writing the interrupt ID it received from the claim to the
> > claim/complete register. The PLIC does not check whether the
> > completion ID is the same as the last claim ID for that target. If
> > the completion ID does not match an interrupt source that is
> > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^
> > completion is silently ignored.  
> 
> Given this bit of the spec...
> 
> > +static void plic_thead_irq_eoi(struct irq_data *d)
> > +{
> > +	struct plic_handler *handler =
> > this_cpu_ptr(&plic_handlers); +
> > +	if (irqd_irq_masked(d)) {
> > +		plic_irq_unmask(d);
> > +		writel(d->hwirq, handler->hart_base +
> > CONTEXT_CLAIM);
> > +		plic_irq_mask(d);
> > +	} else {
> > +		writel(d->hwirq, handler->hart_base +
> > CONTEXT_CLAIM);
> > +	}
> > +}
> > +  
> 
> ... it isn't obvious to me why this cannot happen on an SiFive PLIC.

This indeed happens with SiFive PLIC. I am currently tinkering with
da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However
with changes proposed by Guo Ren in plic_thead_irq_eoi, everything
begins to work fine.

May be these change should be propagated to plic_irq_eoi instead of
making a new function ?

> 
> And it isn't only for threaded interrupts in oneshot mode. Any driver
> can mask an interrupt from its handler after having set the
> IRQ_DISABLE_UNLAZY flag, and the interrupt would need the exact same
> treatment.
> 
> 	M.
> 

---
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive-plic.c index cf74cfa82045..259065d271ef
100644 --- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -163,7 +163,13 @@ static void plic_irq_eoi(struct irq_data *d)
 {
        struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
 
-       writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
+       if (irqd_irq_masked(d)) {
+               plic_irq_unmask(d);
+               writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
+               plic_irq_mask(d);
+       } else {
+               writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
+       }
 }
 
 static struct irq_chip plic_chip = {