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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id o22sm4215280pfu.50.2021.10.28.08.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 08:05:06 -0700 (PDT) Date: Thu, 28 Oct 2021 08:05:06 -0700 (PDT) X-Google-Original-Date: Thu, 28 Oct 2021 08:05:03 PDT (-0700) Subject: Re: [PATCH 0/3] RISC-V: KVM: Few assorted changes In-Reply-To: <62fe1c8e-abe0-5de9-5c00-3549faae1dba@redhat.com> CC: Anup Patel , Paul Walmsley , aou@eecs.berkeley.edu, Atish Patra , anup@brainfault.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org From: Palmer Dabbelt To: pbonzini@redhat.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 28 Oct 2021 07:07:33 PDT (-0700), pbonzini@redhat.com wrote: > On 26/10/21 19:01, Anup Patel wrote: >> I had a few assorted KVM RISC-V changes which I wanted to sent after >> KVM RISC-V was merged hence this series. >> >> These patches can also be found in riscv_kvm_assorted_v1 branch at: >> https://github.com/avpatel/linux.git >> >> Anup Patel (3): >> RISC-V: Enable KVM in RV64 and RV32 defconfigs as a module >> RISC-V: KVM: Factor-out FP virtualization into separate sources >> RISC-V: KVM: Fix GPA passed to __kvm_riscv_hfence_gvma_xyz() functions >> >> arch/riscv/configs/defconfig | 15 ++- >> arch/riscv/configs/rv32_defconfig | 8 +- >> arch/riscv/include/asm/kvm_host.h | 10 +- >> arch/riscv/include/asm/kvm_vcpu_fp.h | 59 +++++++++ >> arch/riscv/kvm/Makefile | 1 + >> arch/riscv/kvm/tlb.S | 4 +- >> arch/riscv/kvm/vcpu.c | 172 --------------------------- >> arch/riscv/kvm/vcpu_fp.c | 167 ++++++++++++++++++++++++++ >> 8 files changed, 244 insertions(+), 192 deletions(-) >> create mode 100644 arch/riscv/include/asm/kvm_vcpu_fp.h >> create mode 100644 arch/riscv/kvm/vcpu_fp.c >> > > Queued 2+3, thanks. Thanks. I'll pick up 1, as per the thread.