Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp2507499pxb; Fri, 29 Oct 2021 02:51:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzCVnIxrtnVA+N4Yt3Vos79pSS3zHyjtYN56k7FYxBSkAnBEXyhKrXdVPEiruMEG4R558z2 X-Received: by 2002:a17:906:48ce:: with SMTP id d14mr12436470ejt.336.1635501119655; Fri, 29 Oct 2021 02:51:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635501119; cv=none; d=google.com; s=arc-20160816; b=sLjFA83xR9hKplJ/ULlaunJMmcKAx1Vy8fv8fgOqWk9q14uPW/6bWcZWfktT1HN2NV BnVGBK10leLxr1mPUBtg/UPxBjA0phxozilSR1Wz6wcqxsDbcqIp0wNjOSVSNEVabUxE qJhtfD7p/jPW9rc6kXvj/mmu7C1ayroxw5o4bROa1I+1o2l0bMOwsW8mSWZUojeBExMz 66W9dg6g/CQ7sFFLcpjh1LNSkgTbuT6MH/oif8zFGSkD6V0XaMy4sEDoDCnb7eAYgOn8 Ke+Kl3asazQbizmdqHCpnmdD8qCHxLRiqirrlZ5NB2Nhakf/vaV9gqHQksc7LWCstv+H nlnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:content-language :in-reply-to:mime-version:user-agent:date:message-id:from:references :cc:to:subject:dmarc-filter:sender:dkim-signature; bh=RXRm3+8WaHCCrhrsAWoMR3rmG9CdF+/zcfwgUU84gEg=; b=hxIdY1wo+ydBVH86VFe1ls/0KTAOCpfOyM8GwhEVFkLzub6n2HNKtFNG8gg+OUJL/W dMaiNksILd9Ll0hYim6i7UKvQPzmgtc8p0lGDi+bEl4IMZxj301a1E4E3pVx5vILI7tf 9uCSJiFYJDHkBpgmQvWjHufc0mQA7OnJN/hxJKKaYbHWqT765UzpJ5jhNs5Nso8J1eN/ MiMjXxOZbfBOUdwweNif4KkyVjFMHoUD1HDKt7APIIg2Sz/ee1zBto0+3KkHfc53GGUI uRRHUPNRgFpCtno6KkytxGHQyRwnYUxbcBKg4GHCY69kynwr5HqG9d3zkZL9znxD7ovc vRCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=rsJF7qG1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p2si6740562ejo.366.2021.10.29.02.51.13; Fri, 29 Oct 2021 02:51:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=rsJF7qG1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231659AbhJ2JvH (ORCPT + 99 others); Fri, 29 Oct 2021 05:51:07 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:63075 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231564AbhJ2JvH (ORCPT ); Fri, 29 Oct 2021 05:51:07 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1635500918; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=RXRm3+8WaHCCrhrsAWoMR3rmG9CdF+/zcfwgUU84gEg=; b=rsJF7qG19JWfcCSxvUXFqLGicRkXkD5kQK4CLnr5f6iqiqn0MNKfS7myFV5If3Ztjq20wxAD apEvuOKVGHnlYiaKAxHNgfhzzRv5gbMtFsozt/Sw2Wsoob50XgtE1fnOBS4utvLkjpLze2Op dF7n3YT6qJBaXOZ37dogIDos4pw= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-west-2.postgun.com with SMTP id 617bc370648aeeca5c7aeb42 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 29 Oct 2021 09:48:32 GMT Sender: rnayak=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C343AC43618; Fri, 29 Oct 2021 09:48:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=2.0 tests=ALL_TRUSTED,BAYES_00, NICE_REPLY_A,SPF_FAIL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from [192.168.1.100] (unknown [49.207.214.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak) by smtp.codeaurora.org (Postfix) with ESMTPSA id CBC24C4338F; Fri, 29 Oct 2021 09:48:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org CBC24C4338F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org Subject: Re: [PATCH v2 1/3] dt-bindings: usb: qcom,dwc3: Add multi-pd bindings for dwc3 qcom To: Bjorn Andersson , Stephen Boyd Cc: Ulf Hansson , Viresh Kumar , Sandeep Maheswaram , Rob Herring , Andy Gross , Greg Kroah-Hartman , Felipe Balbi , Doug Anderson , Matthias Kaehlcke , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, quic_pkondeti@quicinc.com, quic_ppratap@quicinc.com References: From: Rajendra Nayak Message-ID: <5e572c50-d6fe-5a21-d09f-f11a072538c5@codeaurora.org> Date: Fri, 29 Oct 2021 15:18:24 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/29/2021 5:51 AM, Bjorn Andersson wrote: [].. >>> See 266e5cf39a0f ("arm64: dts: qcom: sm8250: remove mmcx regulator") and >>> 3652265514f5 ("clk: qcom: gdsc: enable optional power domain support") >>> >>> MMCX is declared as power-domain for the dispcc (which is correct >>> in itself) and the gdsc code will register GDSCs as subdomains of >>> the same power-domain. >>> >>> >>> To ensure this code path is invoked the clock driver itself needed this >>> 6158b94ec807 ("clk: qcom: dispcc-sm8250: use runtime PM for the clock >>> controller") >>> >>> So at least in theory, considering only USB the minimum would be to >>> pm_runtime_enable() gcc-7280 and add power-domains = to the gcc >>> node. >> >> I'm wary of runtime PM enabling the main clock controller. > > I thought of that as well after sending my last reply. Seems like a good > idea if we can avoid it. > >> Does it work? >> > > Had to test it, but specifying power-domain = in &gcc and adding > the required-opp to the usb node causes CX to enter the given > performance_state. > > So it boots just fine and I didn't pm_runtime_enable() gcc, so > gdsc_pm_runtime_get() will just return. > > That said, I don't grasp all the details happening under the hood, so I > might be missing some details that will bite us when it comes to suspend > or power collapse? > >> I can understand that we need to get the CX power domain pointer into >> the gdsc code somehow, and thus setting the power domain to CX in DT is >> a way to do that. Why do we need to runtime pm enable the clk controller >> though? > > In the case of dispcc we need it because accessing the clock registers > without it crashes the board. > >> Just to make genpd_dev_pm_attach_by_name() hand us a genpd? > > dispcc has a single power-domain so ((struct device*)dispcc)->pm_domain > will automatically be filled out. > >> I >> see in commit 3652265514f5 that we also use it to have gdsc_enable() >> enable the parent domain by using runtime PM to get the clk controller >> and enable the parent domain. That is convoluted. >> > > The purpose of the gdsc_pm_runtime_get() call from gdsc_enable() is to > ensure that the clock controller is powered up, so that we can access > the registers - just as you do in clk_pm_runtime_get() > > So regardless of us changing how the subdomains are setup I think this > part should stay, to work for the clock controllers that need to ensure > their registers are accessible. > >> I'd prefer if we could list that the parent domain is in the registering >> device's power-domain index number, ala clk_parent_data, so that we >> don't have to make the power domain provider into a consumer itself. >> This would clean up the gdsc code so that it doesn't have to go from the >> provider's genpd enable through the provider device to the parent power >> domain enable. Obviously it works but it's hard to follow. >> > > Giving it another look I think the current implementation in gdsc.c will > enable the parent power-domain twice; once in the core because of the > dependency from the subdomain and one by the device itself. > > That said, I do find this technically correct for the dispcc case - > MDSS_GDSC has a vote and dispcc has another vote. > > > I don't have any objections to replacing the current > pd_to_genpd(dev->pm_domain) in gdsc's call to pm_genpd_add_subdomain() > with something carrying information from the clock driver indicating > which of the multiple power domains the gdsc should be parented by. > >>> >>> >>> The "problem" I described would be if there are GDSCs that are >>> subdomains of MX - which I've seen hinted in some documentation. If so >>> we should to specify both CX and MX as power-domains for &gcc and the >>> gdsc implementation needs to be extended to allow us to select between >>> the two. >>> >>> For this I believe a combination of genpd_dev_pm_attach_by_name() and >>> of_genpd_add_subdomain() would do the trick. >>> >>> That is, if there actually are GDSCs exposed by gcc that are not >>> subdomains of CX - otherwise none of this is needed. >>> >> >> Rajendra can correct me, but I believe every device that has a GDSC >> gating power to it is actually inside CX and MX. The CX is for digital >> logic (think registers and interrupts, fetching data from the bus, etc.) >> and the MX is for memories (think flops that retain state of registers Thats true in general but for devices specifically in GCC I doubt anything is part of MX. For the Multimedia ones, yes there is a CX/MX split. >> and internal state of the device). In more modern SoCs they've split >> multimedia (MMCX) and GPU (gpu_gx) out of CX and supply it with a >> different voltage supply and pin on the SoC package. Historically, MX >> voltage has been maintained by the power manager, RPM or RPMh, so that >> when CX is changed, MX >= CX constraints are maintained. I think that >> also changed over time though and MX had to be controlled in addition to >> CX on some firmwares. I recall we had some constraint code that bumped >> up MX whenever CX got higher than it. Having to control both led to more >> round trip time when changing clk rates though so it got combined on the >> backend so that only one message had to be sent to the RPM. >> > > That would explain the current hack(?) in rpmhpd.c which states that mx > is the parent of cx - which I presume is there to say that "mx needs to > be on when cx is on". I always thought we did this only on sdm845, but now that I looked at the code again, I realized we ended up reusing those struct definitions and now that applies to all supported SoCs :/ I will double check but FWIK it should be needed only on sdm845, I will send in a patch to fix that once I get that confirmed. That said the constraints of MX >= CX exist on all SoCs but like Stephen mentioned its expected to be taken care of by RPMh, on sdm845 though for whatever reason that got pushed onto the clients. > As a side effect of all this magic though this means that my vote from > usb is actually applied to MX as well (as would it in Sandeep's original > proposal)... right, that should not be needed from clients, RPMh should be able to handle that internally >> We probably ought to list both CX and MX as power-domains on the clk >> nodes that provide GDSCs to match the hardware. Then we need to know >> which power domain each GDSC wants to set a minimum level on. That would >> be the most correct way to do it. > > As we describe multiple power-domains we won't get dev->pm_domain filled > out for us, so we need to genpd_dev_pm_attach_by_{id,name}() to get the > struct devices for each power-domain and then use those when setting up > the subdomain for each gdsc. > > But per the current implementation (with the CX votes trickling down to > MX as well) we should be able to just grab genpd_dev_pm_attach_by_id(0) > in gdsc_register() and use that if dev->pm_domain isn't set - at least > until we explicitly need to vote for MX only... Atleast for GCC I think it makes sense to have only CX (since nothing should be powered by MX), for some of the other MM controllers if it makes sense we could perhaps look at having both, again in case we really need to explicitly vote on MX, which I haven't seen even in downstream code (barring the sdm845 hack) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation