Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp485164pxb; Fri, 29 Oct 2021 13:46:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpdcJZxeDtbwv89on/cmF7a7rpCGadC23a05IJWXiGR6jSd5RFvsSTiqk53RU3WZMFx5Xw X-Received: by 2002:a05:6602:280a:: with SMTP id d10mr9419896ioe.216.1635540367014; Fri, 29 Oct 2021 13:46:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635540367; cv=none; d=google.com; s=arc-20160816; b=rqpDZJ7pjEjjILbWnP1bSZgc1bd8lYY1ayRG/tgniS8tgbxLoKBRhuNhpmPQy9SLkr aqIrIZXge1oBdEpW7nHA0fMbdH4DOdVLJjan/ZEmnanTEjvZenvOtF3k4wx4V71z7QjD 80YntLg1Mjf8cOway+qKFE5ynLbP8OElylBe9rNv8C1UvtOiA8VZ8PFagMVYQPQX2BGr HVx5X9oJDr8Y19zIm2taI9p7Yk2+dYXc6XLRMEcEBnF6P8wIkxwSFN6eyR3E5TvV3+34 j3ZRcpLszxdv3WKrhnoTtLu+9hNP14LaXp0vHmH2+lq0nsOMPoFwzs0EfZa5oPXhAF93 0SWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=khwee+o4BIEXlURemAxOIdbb1MWFYFtT0vHvBw+Nksk=; b=sgVpPjoYJe7wctq5TywqGgi1+r4BUaSzL//m4NYmGUjE/9Ox+zI258fMqCuqRYtHkU NmQvGtIzyyohcuM5gb4nDaDyMO4LFZsoTz3UgxTaMlgpuEie79uQ9Aw28XYKNpiAKBIx YeYbj+T0inBJGGgI3MB2mQJbJfI9JB2vwztd4Fkj0782v5lCE6BX19ktlImN/W5n4ZdJ wJ2gTjaSD/aROej0wMTJwrB2YcEKHWl27qtkHI8DMNnyWx7BByrXKnVEyQeoLUO36n4B cq4qaPUjQzhEmsYPc7vuipob2gynUX57AFf/jl4qEBct5IwZm3jSZim1jnDuTWr1rROJ Xw0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fYHPHD1c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 11si10294338ilx.102.2021.10.29.13.45.53; Fri, 29 Oct 2021 13:46:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fYHPHD1c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230397AbhJ2UrX (ORCPT + 99 others); Fri, 29 Oct 2021 16:47:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230370AbhJ2UrW (ORCPT ); Fri, 29 Oct 2021 16:47:22 -0400 Received: from mail-ua1-x92b.google.com (mail-ua1-x92b.google.com [IPv6:2607:f8b0:4864:20::92b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F580C061766 for ; Fri, 29 Oct 2021 13:44:53 -0700 (PDT) Received: by mail-ua1-x92b.google.com with SMTP id z22so18036747uaq.12 for ; Fri, 29 Oct 2021 13:44:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=khwee+o4BIEXlURemAxOIdbb1MWFYFtT0vHvBw+Nksk=; b=fYHPHD1cpSxD1HuX6GBkp650+K5AQeXGHiyXjEqXajyjaNdVOFxAbt7T8l21wpClyT J9di4Hv7YTgnZOlpN+ge3ymXROyrvAYtful4TOmblnfCk2B+IIEkWDnz6VgcS9qa1l7L Dl9ReFkbVhSU9XPojwjYSjv3yjv/v6N8YlmivGXQ7bRXChw4p4Hgl7vZBrmB93+NT+T/ dfZhvGyp2jhkBPbxdue5NLMG1+IsB0zMbQK5ymHqv4HkDbbK2Gy8PCPGATnCcTfslSIK 0nAECJPlasKxAvdil6RETd4qYR+eq9EJdQRW74O8g+2KL5/pHVgpi5ZQtDT3TuQ4cJ7G oTAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=khwee+o4BIEXlURemAxOIdbb1MWFYFtT0vHvBw+Nksk=; b=H4WUgp0mLsyRAcV2HyfE85/q9nhR1qRTPqglPqa44mM8dKeCsLQBGyDPBpymXWk/FZ KpBYORzsUSba6GEhxzNG0GJ7lBMP02BQdD44DR0ftx1X3lwo0JGOYeWW3PTxE+6bTgNf MOVZhyHDi5gQKEQ7Y1QXtVyEt1lElNRdcx62PNl9L9V7zToSWtuU5V0rhJhikJL3/GFI YXcGphXSn63fizhNFXD5ZCBF4fFuad4NBCmHKlR7KA8oDw5qpNN0gwnRKcSLSA6Ka0om gQit87uUHEaW1mjKOfmYBZnnuMlesPEak80mZTWEsgna5M3X2OEOQ+rKuzAlrXNFDTPr 0kFA== X-Gm-Message-State: AOAM533c9+L+a3DSW28p5VbKo2+zrv7A1HTe1FZiLLxsV8VukOWGl4Ml DRQq5yhqADqGO+5ucEZBxKRBJw6Zd/0UH+cT2DN6jA== X-Received: by 2002:a67:1781:: with SMTP id 123mr15453627vsx.1.1635540292507; Fri, 29 Oct 2021 13:44:52 -0700 (PDT) MIME-Version: 1.0 References: <20211028183527.3050-1-semen.protsenko@linaro.org> <20211028183527.3050-5-semen.protsenko@linaro.org> In-Reply-To: From: Sam Protsenko Date: Fri, 29 Oct 2021 23:44:40 +0300 Message-ID: Subject: Re: [PATCH 4/7] watchdog: s3c2410: Add support for WDT counter enable To: Guenter Roeck Cc: Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , linux-watchdog@vger.kernel.org, devicetree , Linux Kernel Mailing List , linux-arm Mailing List , Linux Samsung SOC Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 29 Oct 2021 at 03:16, Guenter Roeck wrote: > > On 10/28/21 11:35 AM, Sam Protsenko wrote: > > On new Exynos chips (like Exynos850) WDT counter must be enabled to make > > WDT functional. It's done via CLUSTERx_NONCPU_OUT register, in > > CNT_EN_WDT bit. Add infrastructure needed to enable that counter. > > > > Signed-off-by: Sam Protsenko > > --- > > drivers/watchdog/s3c2410_wdt.c | 28 ++++++++++++++++++++++++++++ > > 1 file changed, 28 insertions(+) > > > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > > index 7c163a257d3c..a5ef7171a90e 100644 > > --- a/drivers/watchdog/s3c2410_wdt.c > > +++ b/drivers/watchdog/s3c2410_wdt.c > > @@ -97,12 +97,16 @@ struct s3c2410_wdt; > > * @rst_stat_reg: Offset in pmureg for the register that has the reset status. > > * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog > > * reset. > > + * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. > > + * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. > > * @quirks: A bitfield of quirks. > > * @disable_auto_reset: If set, this function will be called to disable > > * automatic setting the WDT as a reset reason in RST_STAT on CPU reset; uses > > * disable_reg field. > > * @mask_reset: If set, this function will be called to mask WDT reset request; > > * uses mask_reset_reg and mask_bit fields. > > + * @enable_counter: If set, this function will be called to enable WDT counter; > > + * uses cnt_en_reg and cnt_en_bit fields. > > */ > > > > struct s3c2410_wdt_variant { > > @@ -111,9 +115,12 @@ struct s3c2410_wdt_variant { > > int mask_bit; > > int rst_stat_reg; > > int rst_stat_bit; > > + int cnt_en_reg; > > + int cnt_en_bit; > > u32 quirks; > > int (*disable_auto_reset)(struct s3c2410_wdt *wdt, bool mask); > > int (*mask_reset)(struct s3c2410_wdt *wdt, bool mask); > > + int (*enable_counter)(struct s3c2410_wdt *wdt, bool mask); > > Unless there are different enable functions in the future, > the function is unnecessary. This can be handled as feature bit. > Thanks for review. I've reworked all patches to use quirk bits instead of callbacks. Will send v2 soon. > > }; > > > > struct s3c2410_wdt { > > @@ -132,6 +139,7 @@ struct s3c2410_wdt { > > > > static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask); > > static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask); > > +static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en); > > > > static const struct s3c2410_wdt_variant drv_data_s3c2410 = { > > .quirks = 0 > > @@ -246,6 +254,20 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) > > return ret; > > } > > > > +static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) > > +{ > > + const u32 mask_val = 1 << wdt->drv_data->cnt_en_bit; > > BIT() > > > + const u32 val = en ? mask_val : 0; > > + int ret; > > + > > + ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg, > > + mask_val, val); > > + if (ret < 0) > > + dev_err(wdt->dev, "failed to update reg(%d)\n", ret); > > + > > + return ret; > > +} > > + > > static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > > { > > int ret; > > @@ -262,6 +284,12 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > > return ret; > > } > > > > + if (wdt->drv_data->enable_counter) { > > + ret = wdt->drv_data->enable_counter(wdt, en); > > + if (ret < 0) > > + return ret; > > + } > > + > > return 0; > > } > > > > >