Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp625815pxb; Fri, 29 Oct 2021 17:05:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxYrCnqHIauUccGwWfsM3+QnKr7KphxKmgxxltHWx4DWm9gV90LMbuxHwcJXOYsLgUFl8Nc X-Received: by 2002:a17:907:774d:: with SMTP id kx13mr17846442ejc.239.1635552300188; Fri, 29 Oct 2021 17:05:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635552300; cv=none; d=google.com; s=arc-20160816; b=m8+rak1tEeLH10clMnIMfr6NreBDeAPnecx5/xM50ztjWTmUUoTFX8IYda8CNrJQHZ einKuCvresrGIqfAKZ9p4VCgw/1kDSClJAReBms08AyZIcT+Bh07v6gNaO2f8oAtjEFX Da+rHm4PgU8IOOAg6aYKItEEA980D2I6NcPHL1AV2c6DCh7rawNNvt3uELDzuhbNHgDj FpexyZDOm0H+tC4Ow8ulWQuKaVKnFIU/VRVyxk1XcyOhbRa7KDmcOQY3A5U9ZrB8q0cm p3H80w4UiliFB0HmiUxmZeNt0xUNgoJ4tM/fq3LjuiB22bvmdvTKwsvD+kISJx0pQZfj niQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from :dkim-signature; bh=jl0Mely6L4weR8bSYe4b936KJqFueiKv+9RIem6A3xw=; b=p8KQz+zhYNWmLsV7YxWicUezOHXJ3f+aKW1gdii6KxhnRrmoCWFmTUOsqb8IWd0VBB P70qPDMLxHo4Tqk2JhmzMoPoKW5zF5W5DzmzpF6YOx9ZDRLJp2rWrsI0kMcUG0jQHqp4 IRQ8sQYYrK1pZa0E/6yeg8pqUuU3FuZfz/+YStrkHINlO1T3ZUe6DgaX9WkOuWvbJcr8 m0TSUiaWSTFaDuzWhQ12Tp88+Ta7KKkvNuXypBq5PCNphZLuI1dzoCTiaWzTunt+WfdJ QDdwUPGX3u1fiX7ACmjhak+QRdrmRpo02+5GJBEUzzVtaXJIP47SM4EyQBKVpkWDuSn/ 8C6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=nMR07nTT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qk34si12638886ejc.772.2021.10.29.17.04.36; Fri, 29 Oct 2021 17:05:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=nMR07nTT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231717AbhJ3AEr (ORCPT + 99 others); Fri, 29 Oct 2021 20:04:47 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:49424 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229546AbhJ3AEo (ORCPT ); Fri, 29 Oct 2021 20:04:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1635552135; x=1667088135; h=from:to:cc:subject:date:message-id:mime-version; bh=jl0Mely6L4weR8bSYe4b936KJqFueiKv+9RIem6A3xw=; b=nMR07nTTVKGqXCadrqJlRI2wLyBcpyoBC793BEjEYcPPp1N01+fzV2hL 7lXNXNkw3/OVulDJNnyhMNHV4tbVMWrnW7Qe1stBzGZWhySjSS+LfZ4+A mD+qgwH37Cw+mF1g0DWOVSetlLzM+NdFZqebHUMOnxYV7BCqiUxt0Krku U=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 29 Oct 2021 17:02:15 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2021 17:02:14 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Fri, 29 Oct 2021 17:02:14 -0700 Received: from hu-vamslank-sd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Fri, 29 Oct 2021 17:02:13 -0700 From: To: , , , , , , CC: , , , , , Vamsi Krishna Lanka Subject: [PATCH v3 0/3] Add devicetree support for SDX65 Modem and MTP Date: Fri, 29 Oct 2021 17:02:02 -0700 Message-ID: <1635552125-16407-1-git-send-email-quic_vamslank@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vamsi Krishna Lanka Hello, Changes from v2: - Added cmd-db node to the sdx65 dtsi file Changes from v1: - Addressed Bjorn's comments This series adds devicetree support for Qualcomm SDX65 platform and MTP board. This series functionally depends on Add Pdc, GCC and RPMh Clock support series [1] and Add pinctrl support for SDX65 [2] which are under review. With this current devicetree support, the MTP can boot into initramfs shell. Thanks, Vamsi Vamsi krishna Lanka (3): dt-bindings: arm: qcom: Document SDX65 platform and boards ARM: dts: qcom: Add SDX65 platform and MTP board support ARM: dts: qcom: sdx65: Add pincontrol node Documentation/devicetree/bindings/arm/qcom.yaml | 6 + arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 25 +++ arch/arm/boot/dts/qcom-sdx65.dtsi | 222 ++++++++++++++++++++++++ 4 files changed, 255 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/qcom-sdx65-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-sdx65.dtsi -- 2.7.4