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[23.128.96.18]) by mx.google.com with ESMTP id q3si1845974ilv.125.2021.10.30.05.43.01; Sat, 30 Oct 2021 05:43:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BIk7S5Jt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230327AbhJ3MmH (ORCPT + 99 others); Sat, 30 Oct 2021 08:42:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230089AbhJ3MmG (ORCPT ); Sat, 30 Oct 2021 08:42:06 -0400 Received: from mail-vk1-xa2a.google.com (mail-vk1-xa2a.google.com [IPv6:2607:f8b0:4864:20::a2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E038C061714 for ; Sat, 30 Oct 2021 05:39:36 -0700 (PDT) Received: by mail-vk1-xa2a.google.com with SMTP id d130so5922088vke.0 for ; Sat, 30 Oct 2021 05:39:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6BWVd5QSBtmNHqdFIHqNMkh8yS32RlgmgzQWHgLjOEU=; b=BIk7S5Jt5fOttx6WIIVZ4XVMO+4ht7jw3rzpyd4mZD3HIIQ4wH0lVisbqbM3rkraxb 0adAQWNStbetUIcfOku+EpFTBMsVEmmcy1b9LG5yb4lIzUVuws6f42N8bAuDAEOC7inL 3l1fPSPvos+CgQHtAk4yMbCtCoU5f/j9XEUBl26Y+IbRScrzjsbbz2ZLibAcUjddbHJ8 qSA5y/wyG/2p/B2QiAr/LlnZCx4iyv2eSbFHQRrUuVxAg6rVKwsIUw3FOekNySMUFSdo /TDJprrbF8h9CDe5e3uE1dVq48gNGcS1MhON9R9tmo9dcDuXfS11SQtJdAL/Z35SjRtV RCQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6BWVd5QSBtmNHqdFIHqNMkh8yS32RlgmgzQWHgLjOEU=; b=e0y+gXHNuA2x9HPyjTIlNkD9l5Uk30lfh7WDFv91qExMJcZ6V7qSCIJYV+argggbhM Ohw52JRYKsfduHIJc9VVFV/3BlF1sz65zqbY+M7aPBbER8hhocpd1Pu7OtQQXNVgHwQv a4f0v3tQTZnWve3rwsdqh94i2vhpEuRRJM8U3uKq3OURdaynBciZ/W7OSCMn/QiK3Zwx X/uwJE+kpS8od5Dz9bWEItrDXQnVLIPca1j85bfovF+X/hrQHoiR61yQQCoMq+Yq+ufV JiWSA1oh5M9SzQdAk16RizgWVAglqKSzIVjxJAYiPIUbpkwT6WQjISXvBeHSVnRWBwOt Nc8g== X-Gm-Message-State: AOAM533z1ub8RAmffmXfjppGfJlkzzChNH+P2MvJKR0x8U38ODWKfCgX CkY0YXJPCjTMDLAT7tEDSx485PlLLW7nQCXVW90LqA== X-Received: by 2002:a05:6122:da0:: with SMTP id bc32mr17945585vkb.4.1635597575199; Sat, 30 Oct 2021 05:39:35 -0700 (PDT) MIME-Version: 1.0 References: <20211028183527.3050-1-semen.protsenko@linaro.org> <20211028183527.3050-6-semen.protsenko@linaro.org> <51128b74-de5d-1758-282b-1d4c5250a38d@roeck-us.net> In-Reply-To: <51128b74-de5d-1758-282b-1d4c5250a38d@roeck-us.net> From: Sam Protsenko Date: Sat, 30 Oct 2021 15:39:23 +0300 Message-ID: Subject: Re: [PATCH 5/7] watchdog: s3c2410: Introduce separate source clock To: Guenter Roeck Cc: Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , linux-watchdog@vger.kernel.org, devicetree , Linux Kernel Mailing List , linux-arm Mailing List , Linux Samsung SOC Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 29 Oct 2021 at 03:21, Guenter Roeck wrote: > > On 10/28/21 11:35 AM, Sam Protsenko wrote: > > Some Exynos chips (like Exynos850) have dedicated source clock. That > > clock is provided from device tree as "watchdog_src" clock. In such > > case, "watchdog" clock is just a peripheral clock used for register > > interface. If "watchdog_src" is present, use its rate instead of > > "watchdog" for all timer related calculations. > > > > If the "watchdog_src" clock is present, is "watchdog" clock still needed ? > Please state that explicitly, since it is kind of unusual. > Done, I've reworded the commit message. Will send v2 soon, thanks. > Guenter > > > Signed-off-by: Sam Protsenko > > --- > > drivers/watchdog/s3c2410_wdt.c | 33 +++++++++++++++++++++++++++------ > > 1 file changed, 27 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > > index a5ef7171a90e..bfc5872ca497 100644 > > --- a/drivers/watchdog/s3c2410_wdt.c > > +++ b/drivers/watchdog/s3c2410_wdt.c > > @@ -126,6 +126,8 @@ struct s3c2410_wdt_variant { > > struct s3c2410_wdt { > > struct device *dev; > > struct clk *clock; > > + struct clk *clock_src; > > + unsigned long freq_src; > > void __iomem *reg_base; > > unsigned int count; > > spinlock_t lock; > > @@ -213,10 +215,8 @@ MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); > > > > /* functions */ > > > > -static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock) > > +static inline unsigned int s3c2410wdt_max_timeout(unsigned long freq) > > { > > - unsigned long freq = clk_get_rate(clock); > > - > > return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) > > / S3C2410_WTCON_MAXDIV); > > } > > @@ -364,7 +364,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, > > unsigned int timeout) > > { > > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > > - unsigned long freq = clk_get_rate(wdt->clock); > > + unsigned long freq = wdt->freq_src; > > unsigned int count; > > unsigned int divisor = 1; > > unsigned long wtcon; > > @@ -627,13 +627,27 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > > return ret; > > } > > > > + /* "watchdog_src" clock is optional; if it's not present -- just skip */ > > + wdt->clock_src = devm_clk_get(dev, "watchdog_src"); > > + if (!IS_ERR(wdt->clock_src)) { > > + ret = clk_prepare_enable(wdt->clock_src); > > + if (ret < 0) { > > + dev_err(dev, "failed to enable source clock\n"); > > + ret = PTR_ERR(wdt->clock_src); > > + goto err_clk; > > + } > > + wdt->freq_src = clk_get_rate(wdt->clock_src); > > + } else { > > + wdt->freq_src = clk_get_rate(wdt->clock); > > + } > > + > > wdt->wdt_device.min_timeout = 1; > > - wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock); > > + wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->freq_src); > > > > ret = s3c2410wdt_cpufreq_register(wdt); > > if (ret < 0) { > > dev_err(dev, "failed to register cpufreq\n"); > > - goto err_clk; > > + goto err_clk_src; > > } > > > > watchdog_set_drvdata(&wdt->wdt_device, wdt); > > @@ -707,6 +721,10 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > > err_cpufreq: > > s3c2410wdt_cpufreq_deregister(wdt); > > > > + err_clk_src: > > + if (!IS_ERR(wdt->clock_src)) > > + clk_disable_unprepare(wdt->clock_src); > > + > > err_clk: > > clk_disable_unprepare(wdt->clock); > > > > @@ -727,6 +745,9 @@ static int s3c2410wdt_remove(struct platform_device *dev) > > > > s3c2410wdt_cpufreq_deregister(wdt); > > > > + if (!IS_ERR(wdt->clock_src)) > > + clk_disable_unprepare(wdt->clock_src); > > + > > clk_disable_unprepare(wdt->clock); > > > > return 0; > > >