Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp2563776pxb; Sun, 31 Oct 2021 19:24:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy65CpRPGOTidYzDHhDZpVhzw7uwOCd+Njk5kXzOuEJM4Ukh+ZZ6lN9pmZicdEmUtXl4K9y X-Received: by 2002:a17:907:7e83:: with SMTP id qb3mr7244975ejc.469.1635733486048; Sun, 31 Oct 2021 19:24:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635733486; cv=none; d=google.com; s=arc-20160816; b=Vyc59dDlvVh9Xh1uTV0+5SaUqm/6rxRAH0QHw09cT92ikfRc8a8++W0Ecq60NTpHXa J3Zo10/C+r6EIgS7tRWjf4O12hKA3rfLA3tTPPZZOFEys8SFEkSZhxCiOgRIN4b5ZXJV KN9TuKoxI6Ix5VDtJAFaoOuXlzApHxy3FnjnjGFncMI8I59VZkziico2ww3qBdNZAWlr utrgqzhcQZ2flj6P+tvcgkWNp8mDAU1YktsXAcvaqllF9oHJdj34Ay61DRgIXefM0Bsv EgjL820NX845L6BYIIA8sR5TfLj7iwjx44a2OcwjLF/zBRB03dUisgA4tooJuG92q2r/ xfXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=UHJdjlqLBtC/5ijUKn6d5ggVnJSaBJGZUrkdPVnXMcw=; b=ridLiBv+WSogtyVWFP/mv2/2RPoNFCNFnY/IYj7U0iErvmNoPk+4b/B63DMeObl9AN KDyTmmKn/BvqyU1dUJGS2m19Ww3hFG/d0LffPSSR/6ZVLX8yn3va/3EZS6BaQsXpcAy1 U9AhUEZCrm5n9QQJG+ci3N581UVtPCNFf6LMaBvX6r+fRpxna0HmSwtDrJnMy/PsNYYc jpSPN6bUtOwAAfdB1OSj8AEPSFbOuiEpw2vhtFjP6sT/j7hFGVSrcmIQ5756aw7K3V4G ZIrqp37lBX9uLz/RowZ17C+YsxQJz9k+WqlNbfAtaSoCkFvgEWgRr9X970OEaGiFWVGw 3ItQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=fMd3ZfXt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s12si16913594ejc.488.2021.10.31.19.24.22; Sun, 31 Oct 2021 19:24:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=fMd3ZfXt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbhKACXG (ORCPT + 99 others); Sun, 31 Oct 2021 22:23:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:45626 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230222AbhKACXF (ORCPT ); Sun, 31 Oct 2021 22:23:05 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 67A7161077 for ; Mon, 1 Nov 2021 02:20:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635733233; bh=IafejwO8g0dsJcdD0EGcB6iICuhfeqWu6PXS1URW8eA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=fMd3ZfXtabZUeHFQplrpeiqOicoOh9ZVCi/8eenk5EEx/VpokftF2WvYZ90Lhi8sp BZvlG+Rd2dYSBpY8DmyPOqSE1BAOHRj8FFwNoZQVewKIgu8e4OfscNn9u/EoX16ouj c5YogGHGBhVwi92Y5dWx5TqfK1MqwOtBezKDCVViW4xcYql31uKVteyHaUYRKLDRx0 ttGxCAKNT4f/IWbQdMqyTsWzj+/pxOyyg9HtxhFs4Gx64utst1bnKgk0g1U8KkGWY1 ZbVepXHBTd5nUjHAzEKCBtoU3CzjRpkPrWWxQxX6yz1mEWxirhxKNsaxN1qPWh9CSh 6BGDTEDIeDIEw== Received: by mail-ua1-f49.google.com with SMTP id v3so29209037uam.10 for ; Sun, 31 Oct 2021 19:20:33 -0700 (PDT) X-Gm-Message-State: AOAM533NWI3PTD5EXxMRxvHfgXeqmtPwT6/pJu4iLgnvRPW6IcWs2wLK BYbK35397oXscat1n713ZUMp+2eBOgnZ13Bqol4= X-Received: by 2002:a05:6102:510d:: with SMTP id bm13mr6180428vsb.28.1635733232495; Sun, 31 Oct 2021 19:20:32 -0700 (PDT) MIME-Version: 1.0 References: <20211024013303.3499461-1-guoren@kernel.org> <20211024013303.3499461-4-guoren@kernel.org> <87a6ixbcse.wl-maz@kernel.org> <20211028135523.5cf4b66b@redslave.neermore.group> <87sfwl9oxg.wl-maz@kernel.org> In-Reply-To: <87sfwl9oxg.wl-maz@kernel.org> From: Guo Ren Date: Mon, 1 Nov 2021 10:20:21 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT To: Marc Zyngier Cc: Nikita Shubin , Anup Patel , Atish Patra , Thomas Gleixner , Palmer Dabbelt , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 28, 2021 at 10:58 PM Marc Zyngier wrote: > > On Thu, 28 Oct 2021 11:55:23 +0100, > Nikita Shubin wrote: > > > > Hello Marc and Guo Ren! > > > > On Mon, 25 Oct 2021 11:48:33 +0100 > > Marc Zyngier wrote: > > > > > On Sun, 24 Oct 2021 02:33:03 +0100, > > > guoren@kernel.org wrote: > > > > > > > > From: Guo Ren > > > > > > > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the > > > > driver, only the first interrupt could be handled, and continue irq > > > > is blocked by hw. Because the thead,c900-plic couldn't complete > > > > masked irq source which has been disabled in enable register. Add > > > > thead_plic_chip which fix up c906-plic irq source completion > > > > problem by unmask/mask wrapper. > > > > > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > > > > > The PLIC signals it has completed executing an interrupt handler by > > > > writing the interrupt ID it received from the claim to the > > > > claim/complete register. The PLIC does not check whether the > > > > completion ID is the same as the last claim ID for that target. If > > > > the completion ID does not match an interrupt source that is > > > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ > > > > completion is silently ignored. > > > > > > Given this bit of the spec... > > > > > > > +static void plic_thead_irq_eoi(struct irq_data *d) > > > > +{ > > > > + struct plic_handler *handler = > > > > this_cpu_ptr(&plic_handlers); + > > > > + if (irqd_irq_masked(d)) { > > > > + plic_irq_unmask(d); > > > > + writel(d->hwirq, handler->hart_base + > > > > CONTEXT_CLAIM); > > > > + plic_irq_mask(d); > > > > + } else { > > > > + writel(d->hwirq, handler->hart_base + > > > > CONTEXT_CLAIM); > > > > + } > > > > +} > > > > + > > > > > > ... it isn't obvious to me why this cannot happen on an SiFive PLIC. > > > > This indeed happens with SiFive PLIC. I am currently tinkering with > > da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However > > with changes proposed by Guo Ren in plic_thead_irq_eoi, everything > > begins to work fine. > > > > May be these change should be propagated to plic_irq_eoi instead of > > making a new function ? > > That's my impression too. I think the T-Head defect is pretty much > immaterial when you consider how 'interesting' the PLIC architecture > is. Which is the "T-Head defect" you mentioned here? 1. Auto masking with claim + complete (I don't think it's a defect, right? May I add a new patch to utilize the feature to decrease a little duplicate mask/unmask operations in the future?) 2. EOI failed when masked > Conflating EOI and masking really is a misfeature... I think the problem is riscv PLIC reuse enable bit as mask bit. I recommend separating them. That means: - EOI still depends on enable bit. - Add mask/unmask bit regs to do the right thing. > > M. > > -- > Without deviation from the norm, progress is not possible. -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/