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[23.128.96.18]) by mx.google.com with ESMTP id a18si16888815eda.2.2021.11.01.02.36.45; Mon, 01 Nov 2021 02:37:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233485AbhKAJhY (ORCPT + 99 others); Mon, 1 Nov 2021 05:37:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:43700 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233701AbhKAJd7 (ORCPT ); Mon, 1 Nov 2021 05:33:59 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6F42561263; Mon, 1 Nov 2021 09:25:34 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mhTZM-002oth-DA; Mon, 01 Nov 2021 09:25:32 +0000 Date: Mon, 01 Nov 2021 09:25:31 +0000 Message-ID: <87fssg9qic.wl-maz@kernel.org> From: Marc Zyngier To: Guo Ren Cc: Nikita Shubin , Anup Patel , Atish Patra , Thomas Gleixner , Palmer Dabbelt , Heiko =?UTF-8?B?U3TDvGJuZXI=?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT In-Reply-To: References: <20211024013303.3499461-1-guoren@kernel.org> <20211024013303.3499461-4-guoren@kernel.org> <87a6ixbcse.wl-maz@kernel.org> <20211028135523.5cf4b66b@redslave.neermore.group> <87sfwl9oxg.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: guoren@kernel.org, nikita.shubin@maquefel.me, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 01 Nov 2021 02:20:21 +0000, Guo Ren wrote: > > On Thu, Oct 28, 2021 at 10:58 PM Marc Zyngier wrote: > > > > On Thu, 28 Oct 2021 11:55:23 +0100, > > Nikita Shubin wrote: > > > > > > Hello Marc and Guo Ren! > > > > > > On Mon, 25 Oct 2021 11:48:33 +0100 > > > Marc Zyngier wrote: > > > > > > > On Sun, 24 Oct 2021 02:33:03 +0100, > > > > guoren@kernel.org wrote: > > > > > > > > > > From: Guo Ren > > > > > > > > > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the > > > > > driver, only the first interrupt could be handled, and continue irq > > > > > is blocked by hw. Because the thead,c900-plic couldn't complete > > > > > masked irq source which has been disabled in enable register. Add > > > > > thead_plic_chip which fix up c906-plic irq source completion > > > > > problem by unmask/mask wrapper. > > > > > > > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > > > > > > > The PLIC signals it has completed executing an interrupt handler by > > > > > writing the interrupt ID it received from the claim to the > > > > > claim/complete register. The PLIC does not check whether the > > > > > completion ID is the same as the last claim ID for that target. If > > > > > the completion ID does not match an interrupt source that is > > > > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ > > > > > completion is silently ignored. > > > > > > > > Given this bit of the spec... > > > > > > > > > +static void plic_thead_irq_eoi(struct irq_data *d) > > > > > +{ > > > > > + struct plic_handler *handler = > > > > > this_cpu_ptr(&plic_handlers); + > > > > > + if (irqd_irq_masked(d)) { > > > > > + plic_irq_unmask(d); > > > > > + writel(d->hwirq, handler->hart_base + > > > > > CONTEXT_CLAIM); > > > > > + plic_irq_mask(d); > > > > > + } else { > > > > > + writel(d->hwirq, handler->hart_base + > > > > > CONTEXT_CLAIM); > > > > > + } > > > > > +} > > > > > + > > > > > > > > ... it isn't obvious to me why this cannot happen on an SiFive PLIC. > > > > > > This indeed happens with SiFive PLIC. I am currently tinkering with > > > da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However > > > with changes proposed by Guo Ren in plic_thead_irq_eoi, everything > > > begins to work fine. > > > > > > May be these change should be propagated to plic_irq_eoi instead of > > > making a new function ? > > > > That's my impression too. I think the T-Head defect is pretty much > > immaterial when you consider how 'interesting' the PLIC architecture > > is. > Which is the "T-Head defect" you mentioned here? > 1. Auto masking with claim + complete (I don't think it's a defect, > right? May I add a new patch to utilize the feature to decrease a > little duplicate mask/unmask operations in the future?) That *is* a T-Head defect. It may not be material for Linux, but being a departure from the spec, it is a bug, clear and simple. IMHO, either you implement the spec to the letter, or you don't. If you deviate, this is something else. > 2. EOI failed when masked This one is a PLIC architecture defect, which seems to plague everyone. > > > Conflating EOI and masking really is a misfeature... > I think the problem is riscv PLIC reuse enable bit as mask bit. I > recommend separating them. That means: > - EOI still depends on enable bit. > - Add mask/unmask bit regs to do the right thing. Maybe, but that's not the problem at hand. I suggest you move architectural discussions to a separate thread, and keep this thread for fixing the mess that plagues existing users. M. -- Without deviation from the norm, progress is not possible.