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Date:   Mon, 1 Nov 2021 13:27:11 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>
Cc:     Russell King <linux@armlinux.org.uk>, Andrew Lunn <andrew@lunn.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        Gregory Clement <gregory.clement@bootlin.com>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup
Message-ID: <20211101162711.GA2744544@nvidia.com>
References: <20211101150405.14618-1-pali@kernel.org>
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 =?utf-8?B?YzFXTStPVmpOKzkwdWFhb2MwaDNyTTROd1g1YUlwQ3VkbG1YSFlFenJ5Zjhy?=
 =?utf-8?B?Q0NqYXc4ajlnL3IxbGc0c2tMbmFVTXpURkZrbjNQSmVteHhiY0hxdHE4dzFE?=
 =?utf-8?B?bHFTSGN4ZEdoUXlEcTh4TmdMMGd6b0RyTW9RMnFpaGlNOFJFc0N0cHBsRXR2?=
 =?utf-8?B?dE5CcmJDR2hDNi9laUdqUWlUbVAzRnJsTFhsM0ZDZCtwWFNaaXpZMThaenhj?=
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 =?utf-8?B?RnhXZXBkMmdYUG53bWVudE5XQ2xidEF5cFZLaWtZczNid3RUN0paN0ZYVWlR?=
 =?utf-8?B?YVAxOXFYK0lldWZSSmxaanRjYkJNTlJNMUQxa1o4VE1GWFFkM040UnAxSnBC?=
 =?utf-8?B?T0dienoyc1FjMjdLZVB5YUJMV3VNQi9rZStzTzFrQ2NDcVBSVlF1eHl0VVlG?=
 =?utf-8?B?Nll2MmlyR3pHK0JRM2llVnFnME4rb1VPcjUyNGRiY3FzcWIvdFphcHRQWENR?=
 =?utf-8?B?QnJ6SWxTY2w0NUhCM2FyaVk0VFRjdkM1MmNZektEdHNFbWhFSzNXOWUwK09C?=
 =?utf-8?B?MEt1blFLRmpKQXU1QzFyQ1doTjlldjlKSStkMWx0WmVQR0VMWTI2NHlFMCtM?=
 =?utf-8?B?RmJWTkZqL0dad3FlQkx5Z2RxN0NocDhDdmxXdWFXSzlieVVUWWpKNWRjNmwz?=
 =?utf-8?B?aEJrZzlzTENNYzhvNml1OWdXVUNBdHRGcVdYSjZvR1QzK09GN2R5MHl0bXQy?=
 =?utf-8?B?TWRWLzZEVTVpWldEQ245cGhZMkJHUlNnbkxzZkxtMnJiMFNqWmtjN3hNQ3hy?=
 =?utf-8?B?RkR0bmRkNGt5bGplOTVoVDVKcjd4WmVES3dDOXZzK29mbFpkdE9nTDlkNWcz?=
 =?utf-8?B?UVI1ejdwbFBtZ1haS1FmTFdCdnpFckc0VXg3cTVEVm52NlAxUmZ1amZ2dHNz?=
 =?utf-8?B?TXJGSWtac2dCeVBEVVZrRktDdlhMZWZmQWZXa2pveDdEaDQxd3Y5a3Q5dm5k?=
 =?utf-8?B?QkwzWjJUMHViYTc3KzkyTmxiODNXVzJtOUdYUFFIMUc4QUJpTHdnRFpEVEph?=
 =?utf-8?B?ZmtHUWI1YnBQamxRR2t4Z29MZklja3QvSUs0MWk4QlUxTDU1R05XdTU4WVd5?=
 =?utf-8?B?OWpHR3hCeU9weFRhYmhwZmtuTGZwN1Z0TG1haU9OVi9mV1hZL1A4ZFdNdzNF?=
 =?utf-8?B?MlpyYkJ5V2pQck80WmFQSElRb21LcDgxNmk1TlBNbGEwekw0S2tLZzZmK1hJ?=
 =?utf-8?B?aFJ0d3I5c0NsT21jZFAxQzZHT0Rrak1lbFlFYWRLT1RUSVVsYm9EQytTU0x0?=
 =?utf-8?Q?IGJM=3D?=
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On Mon, Nov 01, 2021 at 04:04:05PM +0100, Pali Rohár wrote:
> - The code relies on rc_pci_fixup being called, which only happens
>   when CONFIG_PCI_QUIRKS is enabled, so add that to Kconfig. Omitting
>   this causes a booting failure with a non-obvious cause.
> - Update rc_pci_fixup to set the class properly, copying the
>   more modern style from other places
> - Correct the rc_pci_fixup comment
> 
> This patch just re-applies commit 1dc831bf53fd ("ARM: Kirkwood: Update
> PCI-E fixup") for all other Marvell platforms which use same buggy PCIe
> controller.

I wonder if that code is even relevant any more since we started using
CONFIG_PCI_MVEBU

?

Really, these broken controllers should not be used "raw" but always
via their special host bridge driver that fixes all the config space
problems.

Jason